公开(公告)号：US5878049A

公开(公告)日：1999-03-02

申请号：US840056

申请日：1997-04-24

申请人： Luigi Pascucci

发明人： Luigi Pascucci

IPC分类号： G11C7/22 ,  G06F11/00

CPC分类号： G11C7/22

摘要： A circuit for read-enabling a memory device with checking of the minimum functionality conditions of the memory cells and reading circuits, particularly for non-volatile memories, having a structure for reproducing the operating conditions within the memory matrix to determine the minimum duration of the step for pre-charging the bit lines involved in the reading operation, the structure being adapted to generate a pre-charge step interruption signal that depends on the reaching of the minimum functionality conditions; a mechanism for generating a power-on-reset signal for enabling reading when the minimum functionality conditions for reading correctness are reached, the power-on-reset signal generating mechanism being adapted to drive a control logic mechanism as well as a reading control and stimulation mechanism. The circuit further includes a memory mechanism for the pre-charge step, which is driven by the structure for reproducing the operating conditions within the memory matrix, by the control logic mechanism, and by the reading control and stimulation mechanism, the memory mechanism for the pre-charge step causing, at the onset of the minimum functionality conditions, the end of the pre-charge step to perform a first reading of the memory cells in assured conditions.

摘要翻译： 一种用于通过检查具有用于再现存储器矩阵内的操作条件的结构的存储器单元和读取电路的特别是用于非易失性存储器的读取电路的最小功能条件来读取存储器件的电路，以确定存储器单元和读取电路的最小持续时间 该步骤用于对涉及读取操作的位线进行预充电，该结构适于产生取决于达到最小功能条件的预充电步骤中断信号; 当达到读取正确性的最小功能条件时，产生用于使能读取的上电复位信号的机构，所述上电复位信号产生机构适于驱动控制逻辑机制以及读取控制和刺激 机制。 电路还包括用于预充电步骤的存储机构，其由用于通过控制逻辑机制再现存储器矩阵内的操作条件的结构驱动，并且通过读取控制和刺激机制，用于 预充电步骤在最小功能条件开始时导致预充电步骤的结束，以在保证条件下执行存储器单元的第一读取。

公开(公告)号：US5864513A

公开(公告)日：1999-01-26

申请号：US827409

申请日：1997-03-27

申请人： Luigi Pascucci

发明人： Luigi Pascucci

IPC分类号： G11C16/28 ,  G11C13/00

CPC分类号： G11C16/28

摘要： A system for determining the programmed/non-programmed status of a memory cell includes a first branch for connecting a first load and a memory cell matrix and a second branch for connecting a second load and at least one virgin reference memory cell. A circuit for selecting a memory cell of the memory matrix and a circuit for selecting at least one virgin reference cell are included. Each one of the first and second branches has a transistor for enabling a flow of current, respectively, between the first load and the second load and the memory cell matrix and the at least one reference memory cell. The enabling transistors are controlled, respectively, by a first biasing structure and by a second biasing structure. The system includes at least one transistor for redistributing the current of the load on the first branch, which is connected in parallel to the enabling transistor, and a first equalization transistor that is controlled by a precharge signal for the equalization of opposite nodes of the first and second branches. The at least one current redistribution transistor provides a current imbalance in the first load and in the second load in order to sense a difference in conductivity between a memory cell of the memory matrix and the at least one reference cell in order to determine the programmed or non-programmed status of the memory cell of the memory matrix.

摘要翻译： 用于确定存储器单元的编程/非编程状态的系统包括用于连接第一负载和存储单元矩阵的第一分支和用于连接第二负载和至少一个处女参考存储单元的第二分支。 包括用于选择存储器矩阵的存储单元的电路和用于选择至少一个处女参考单元的电路。 第一和第二分支中的每一个分支具有晶体管，用于分别在第一负载和第二负载与存储单元矩阵和至少一个参考存储单元之间流动电流。 分别通过第一偏压结构和第二偏压结构来控制使能晶体管。 该系统包括至少一个晶体管，用于重新分配与启用晶体管并联连接的第一分支上的负载电流，以及由预充电信号控制的第一均衡晶体管，用于均衡第一 和第二分支。 所述至少一个电流再分配晶体管在第一负载和第二负载中提供电流不平衡，以便感测存储器矩阵的存储单元与至少一个参考单元之间的导电差异，以便确定编程或 存储器矩阵的存储单元的非编程状态。

公开(公告)号：US5864500A

公开(公告)日：1999-01-26

申请号：US835296

申请日：1997-04-07

申请人： Luigi Pascucci

发明人： Luigi Pascucci

IPC分类号： G11C14/00 ,  G11C11/34

CPC分类号： G11C14/00

摘要： The present invention concerns an auto-saving circuit for programming configuration elements of non-volatile memory cells organized in a cells matrix in a memory device integrated on a semiconductor. The auto-saving circuit is inserted between a first and a second power supply reference voltage and is powered also by programming voltages generated inside the memory device to produce at an output programming signals of the configuration elements. The auto-saving circuit includes a first and a second circuit portion, one for each signal output and each powered by a respective programming voltage and each including a switching network with at least one high threshold transistor and decoupling elements to give inertia to the circuit against electrostatic discharges or accidental power supply variations.

摘要翻译： 本发明涉及用于编程组合在集成在半导体上的存储器件中的单元矩阵中的非易失性存储单元的配置元件的自动保存电路。 自动保存电路插入在第一和第二电源参考电压之间，并且还通过在存储器件内部产生的编程电压来供电，以在配置元件的输出编程信号产生。 自动保存电路包括第一和第二电路部分，每个信号输出一个，每个由相应的编程电压供电，每个包括具有至少一个高阈值晶体管和去耦元件的开关网络，以使电路的惯性反对 静电放电或意外电源变化。

公开(公告)号：US5850361A

公开(公告)日：1998-12-15

申请号：US628587

申请日：1996-04-04

申请人： Luigi Pascucci

发明人： Luigi Pascucci

IPC分类号： G11C16/04 ,  G11C29/00

CPC分类号： G11C29/802 ,  G11C16/0433

摘要： A coding device including an array of multibit registers, each being composed of a plurality of programmable nonvolatile memory cells connected to an OR configuration to a common sensing line of the register to which a single reading circuit is associated. A first, select/enable bus (SELbus) controls the connection of only one at a time of said programmable memory cells to said common sensing line of each multibit register. To each wire of a second, configuring bus (CODE bus) are connected in common the current terminals of as many programming transistors as the memory cells that compose each register, and to each wire of a third, contingently programming bus (PG bus) are connected the gates of the programming transistors of memory cells of the same order of said registers.

摘要翻译： 一种包括多位寄存器阵列的编码装置，每一个由多个可编程非易失性存储单元构成，所述多个可编程非易失存储单元连接到与配置相关联的寄存器的公共感测线的OR配置。 第一个选择/使能总线（SELbus）控制所述可编程存储器单元每次只有一个与每个多位寄存器的所述公共感测线的连接。 对于一秒钟的每根线，配置总线（CODE总线）与构成每个寄存器的存储器单元的编程晶体管的当前端子共同连接，并且第三个偶然编程总线（PG总线）的每个线都是 连接所述寄存器相同顺序的存储器单元的编程晶体管的栅极。

公开(公告)号：US5847584A

公开(公告)日：1998-12-08

申请号：US688956

申请日：1996-07-31

申请人： Luigi Pascucci

发明人： Luigi Pascucci

IPC分类号： G05F1/571 ,  G11C5/14 ,  H03K5/22

CPC分类号： G05F1/571 ,  G11C5/14 ,  G11C5/143

摘要： A threshold detecting device including a detecting stage having a first input supplied with a monitored voltage varying between a first and second value, a second input supplied with a reference voltage by a reference source stage, and an output supplying a logic signal indicating crossover of a predetermined threshold by the monitored voltage. Initially, the reference source stage is off and the reference voltage follows the course of the monitored voltage; upon the monitored voltage exceeding a first threshold value, the reference source is turned on and causes the reference voltage to rise more slowly than the monitored voltage, so that an increasing voltage difference is present between the first and second inputs of the reference stage; and, upon the voltage difference exceeding a second threshold value, the detecting stage switches and generates the threshold crossover signal.

摘要翻译： 一种阈值检测装置，包括检测级，该检测级具有提供有在第一和第二值之间变化的监控电压的第一输入，由参考源极级提供参考电压的第二输入和提供逻辑信号的输出， 通过监测电压的预定阈值。 最初，参考源级关闭，参考电压跟随监控电压的过程; 在监测电压超过第一阈值时，参考源导通，使参考电压比监视电压上升得更慢，从而在参考级的第一和第二输入之间存在增加的电压差; 并且当电压差超过第二阈值时，检测级切换并产生阈值交叉信号。

公开(公告)号：US5815457A

公开(公告)日：1998-09-29

申请号：US659665

申请日：1996-06-06

申请人： Luigi Pascucci

发明人： Luigi Pascucci

IPC分类号： G11C11/413 ,  G11C8/10 ,  G11C8/00

CPC分类号： G11C8/10

摘要： A bit line selection decoder for an electronic memory having a plurality of bit lines in a plurality of groups includes a first set of a plurality of switches, each switch for selecting one of the plurality of bit lines in response to a control signal from a set of control lines applied to each group of bit lines. A second set of a plurality of switches is provided wherein each switch selects one group of the plurality of bit lines. The bit line selection decoder also includes a decoder which has a first input bus of control lines and a second input bus of control lines, wherein the control lines from the first and second input bus address any one of the plurality of groups of bit lines. The decoder has a plurality of outputs, wherein each output drives one switch in the second set of switches. The decoder may include a plurality of modules. Each module has a first input connected to receive one of the control lines from the second bus and a second input connected to receive the control lines of the first bus. The module includes a mechanism for activating a first output according to a combination of the first input and one of the control lines from the second input and a mechanism for activating a second output according to a combination of the first input and another of the control lines from the second input.

摘要翻译： 一种用于具有多个组中的多个位线的电子存储器的位线选择解码器包括多个开关的第一组，每个开关用于响应于来自一组的控制信号来选择多个位线之一 的控制线应用于每组位线。 提供了第二组多个开关，其中每个开关选择多个位线中的一组。 位线选择解码器还包括具有控制线的第一输入总线和控制线的第二输入总线的解码器，其中来自第一和第二输入总线的控制线寻址多组位线中的任意一组。 解码器具有多个输出，其中每个输出驱动第二组开关中的一个开关。 解码器可以包括多个模块。 每个模块具有连接以从第二总线接收控制线之一的第一输入和连接以接收第一总线的控制线的第二输入。 该模块包括用于根据来自第二输入的第一输入和控制线中的一个的组合来激活第一输出的机构，以及用于根据第一输入和另一个控制线的组合来激活第二输出的机构 从第二个输入。

公开(公告)号：US5815437A

公开(公告)日：1998-09-29

申请号：US813171

申请日：1997-03-07

申请人： Luigi Pascucci ,  Antonio Barcella ,  Paolo Rolandi ,  Marco Fontana

发明人： Luigi Pascucci ,  Antonio Barcella ,  Paolo Rolandi ,  Marco Fontana

IPC分类号： G11C17/00 ,  G11C7/10 ,  G11C16/02 ,  G11C16/06 ,  G11C29/00 ,  G11C11/34 ,  G11C7/00

CPC分类号： G11C29/70 ,  G11C7/10

摘要： A data input/output managing device, particularly for non-volatile memories that comprise at least one matrix of memory cells. The managing device comprises: at least one bidirectional internal bus for the transfer of data from and to the memory; a redundancy management line that is associated with the internal bus; means for enabling/disabling the transmission, over the internal bus, of the data from the memory toward the outside; means for enabling/disabling access to the internal bus on the part of data whose source is other than the memory matrix, for transmission to the memory matrix; and means for enabling/disabling the connection between the outside of the memory and the redundancy line during the reading of the memory matrix and during its programming.

摘要翻译： 一种数据输入/输出管理装置，特别是包括至少一个存储器单元矩阵的非易失性存储器。 管理设备包括：至少一个双向内部总线，用于将数据从存储器传送到存储器; 与内部总线相关联的冗余管理线; 用于启用/禁用内部总线上的数据从存储器向外部的传输的装置; 用于启用/禁用其源不同于存储器矩阵的数据部分访问内部总线的装置，用于传输到存储器矩阵; 以及用于在读取存储器矩阵期间和在其编程期间启用/禁用存储器外部与冗余线之间的连接的装置。

公开(公告)号：US5793699A

公开(公告)日：1998-08-11

申请号：US811386

申请日：1997-03-04

申请人： Luigi Pascucci

发明人： Luigi Pascucci

IPC分类号： G11C8/18 ,  G11C8/00

CPC分类号： G11C8/18

摘要： A circuit for generating and resetting timing signals used for reading a memory device, includes first detecting circuit means for detecting a state transition of address digital signals of the memory device, the detecting means being suitable of generating a start digital signal of a read operation represented by a digital pulse of a prescribed duration upon a state transition of at least one of said address signals, second circuit means activated by said start signal for generating a timing signal for the read operation of the memory device, and third circuit means driven by said start digital signal for generating resetting signals for said timing signals, and fourth circuit means for detecting than said start signal has a duration shorter that said prescribed duration and for determining a consequent extension of the duration of said start signal sufficient to assure the generation of said resetting signals.

摘要翻译： 一种用于产生和复位用于读取存储器件的定时信号的电路，包括用于检测存储器件的地址数字信号的状态转换的第一检测电路装置，该检测装置适于产生表示的读取操作的起始数字信号 通过在至少一个所述地址信号的状态转换时的规定持续时间的数字脉冲，由所述起始信号激活的第二电路装置，用于产生用于存储器件的读取操作的定时信号;以及第三电路装置， 启动用于产生用于所述定时信号的复位信号的数字信号，以及用于比所述起始信号检测的第四电路装置具有比所述规定持续时间短的持续时间，并且用于确定所述起始信号的持续时间的延续足以确保产生所述 复位信号。

公开(公告)号：US5737268A

公开(公告)日：1998-04-07

申请号：US684431

申请日：1996-07-19

申请人： Luigi Pascucci

发明人： Luigi Pascucci

IPC分类号： G11C11/4091 ,  G11C7/00

CPC分类号： G11C11/4091

摘要： A latch arrangement, having a load, receives an equalization signal to control the timing of data sensing and data capture. The slope of the equalization signal is modulated so that it has two slopes: a less steep one which permits evaluation of a datum with appropriate caution, and a much steeper slope, which occurs at the end of reliable evaluation, to capture the datum and store it. The equalization signal is generated by first presetting the equalization signal to a first value. Thereafter a change in the equalization signal from the first value to a second value is initiated. After initiating the change in the equalization signal, the equalization signal is slowly discharged at a first slope. A ratio between a current generated in a generic matrix cell applied to the load of the latch arrangement and a reference current is evaluated. When the evaluated ratio reaches a desired level, the equalization signal is quickly discharged to the second value at a second slope.

摘要翻译： 具有负载的锁存装置接收均衡信号以控制数据检测和数据捕获的定时。 调整均衡信号的斜率，使其具有两个斜率：较不陡的斜率，允许在适当谨慎的情况下对基准进行评估，并且在可靠评估结束时出现更陡峭的斜率，以捕获基准和存储 它。 通过首先将均衡信号预设为第一值来产生均衡信号。 此后，启动从第一值到第二值的均衡信号的改变。 在启动均衡信号的变化之后，均衡信号以第一斜率缓慢放电。 评估在施加到锁存装置的负载的一般矩阵单元中产生的电流与参考电流之间的比率。 当评估比达到期望水平时，均衡信号以第二斜率快速地排放到第二值。

公开(公告)号：US5708604A

公开(公告)日：1998-01-13

申请号：US789616

申请日：1997-01-27

申请人： Marco Fontana ,  Luigi Pascucci

发明人： Marco Fontana ,  Luigi Pascucci

IPC分类号： G11C8/08 ,  G11C16/06

CPC分类号： G11C8/08

摘要： A driving circuit for a final decoding stage of an EPROM, EEPROM or FLASH EPROM for battery powered apparatuses functioning at relatively low supply voltage avoids energy absorption from a commonly boosted voltage node by switching the capacitance of the control node of the p-channel pull-up device of the CMOS inverter that drives the memory line and which constitutes the load of the driving circuit. The node is effectively charged by drawing current from the supply node and is discharged rapidly by switching in parallel thereto a previously discharged capacitance. This charge-sharing switcheable capacitance may advantageously be the capacitance of a similar p-channel pull-up control node of a deselected wordline of the array.

摘要翻译： 用于在较低电源电压下工作的电池供电设备的EPROM，EEPROM或FLASH EPROM的最终解码级的驱动电路通过切换p沟道下拉单元的控制节点的电容来避免来自共同升压的电压节点的能量吸收， 该CMOS反相器驱动存储器线并构成驱动电路的负载。 该节点通过从电源节点引出电流被有效地充电，并且通过并联地切换预先放电的电容而迅速放电。 该电荷共享可切换电容可以有利地是阵列的未选择的字线的类似的p沟道上拉控制节点的电容。