公开(公告)号：US06438669B2

公开(公告)日：2002-08-20

申请号：US08813687

申请日：1997-03-07

申请人： Luigi Pascucci ,  Paolo Rolandi ,  Marco Fontana ,  Antonio Barcella

发明人： Luigi Pascucci ,  Paolo Rolandi ,  Marco Fontana ,  Antonio Barcella

IPC分类号： G06F1300

CPC分类号： G11C7/1006

摘要： A non-volatile memory device that comprises an internal bus for the transmission of data and other information of the memory to output pads; a timer; and an enabling/disabling circuit for enabling and disabling access to the internal bus; the timer controlling the internal bus to transmit information signals of the memory device that originate from local auxiliary lines over the internal bus when the bus is in an inactive period during a normal memory data reading cycle; the timer controlling the enabling/disabling means to allow/deny access to the internal bus on the part of the information signals or of the data from or to the memory.

摘要翻译： 一种非易失性存储器件，包括用于将数据和存储器的其它信息传输到输出焊盘的内部总线; 一个计时器 以及用于启用和禁用访问内部总线的启用/禁用电路; 所述定时器控制所述内部总线，以在所述总线在正常存储器数据读取周期期间处于非活动时段期间，通过所述内部总线发送来自所述本地辅助线路的存储器件的信息信号; 所述定时器控制所述启用/禁用装置允许/拒绝部分所述信息信号或来自所述存储器的数据的所述内部总线的访问。

公开(公告)号：US06175521B1

公开(公告)日：2001-01-16

申请号：US08833336

申请日：1997-04-04

申请人： Luigi Pascucci ,  Marco Fontana

发明人： Luigi Pascucci ,  Marco Fontana

IPC分类号： G11C1604

CPC分类号： G11C16/30

摘要： A voltage regulator for programming electrically programmable non-volatile memory cells in a cell matrix that is divided in segments. The voltage regulator includes an amplifier stage connected and powered between a first reference voltage and a second reference voltage and having a first input terminal connected to a voltage divider of the first reference voltage, an output terminal connected to the control terminal of a MOS transistor which has a conduction terminal connected to the memory cells through a programming line, and a second input terminal connected to the programming line, and connected to the output terminal in a feedback loop. The voltage regulator includes an input circuit portion made up of active elements and inserted in turn between the first and second reference voltages. The input circuit portion connects the amplifier to the first reference voltage in response to at least one pair of signals to activate the voltage regulator only when there is at least one cell to be programmed in the segment that is associated with the regulator.

摘要翻译： 一种电压调节器，用于对细分矩阵中的电可编程非易失性存储器单元进行编程，该单元矩阵被分段。 电压调节器包括在第一参考电压和第二参考电压之间连接并供电并且具有连接到第一参考电压的分压器的第一输入端的放大器级，连接到MOS晶体管的控制端的输出端， 具有通过编程线连接到存储器单元的导电端子和连接到编程线的第二输入端子，并且在反馈回路中连接到输出端子。 电压调节器包括由有源元件构成的输入电路部分，并依次插入在第一和第二参考电压之间。 响应于至少一对信号，输入电路部分将放大器连接到第一参考电压，以便仅当在与调节器相关联的段中存在要编程的至少一个单元时激活电压调节器。

公开(公告)号：US5815437A

公开(公告)日：1998-09-29

申请号：US813171

申请日：1997-03-07

申请人： Luigi Pascucci ,  Antonio Barcella ,  Paolo Rolandi ,  Marco Fontana

发明人： Luigi Pascucci ,  Antonio Barcella ,  Paolo Rolandi ,  Marco Fontana

IPC分类号： G11C17/00 ,  G11C7/10 ,  G11C16/02 ,  G11C16/06 ,  G11C29/00 ,  G11C11/34 ,  G11C7/00

CPC分类号： G11C29/70 ,  G11C7/10

摘要： A data input/output managing device, particularly for non-volatile memories that comprise at least one matrix of memory cells. The managing device comprises: at least one bidirectional internal bus for the transfer of data from and to the memory; a redundancy management line that is associated with the internal bus; means for enabling/disabling the transmission, over the internal bus, of the data from the memory toward the outside; means for enabling/disabling access to the internal bus on the part of data whose source is other than the memory matrix, for transmission to the memory matrix; and means for enabling/disabling the connection between the outside of the memory and the redundancy line during the reading of the memory matrix and during its programming.

摘要翻译： 一种数据输入/输出管理装置，特别是包括至少一个存储器单元矩阵的非易失性存储器。 管理设备包括：至少一个双向内部总线，用于将数据从存储器传送到存储器; 与内部总线相关联的冗余管理线; 用于启用/禁用内部总线上的数据从存储器向外部的传输的装置; 用于启用/禁用其源不同于存储器矩阵的数据部分访问内部总线的装置，用于传输到存储器矩阵; 以及用于在读取存储器矩阵期间和在其编程期间启用/禁用存储器外部与冗余线之间的连接的装置。

公开(公告)号：US5708604A

公开(公告)日：1998-01-13

申请号：US789616

申请日：1997-01-27

申请人： Marco Fontana ,  Luigi Pascucci

发明人： Marco Fontana ,  Luigi Pascucci

IPC分类号： G11C8/08 ,  G11C16/06

CPC分类号： G11C8/08

摘要： A driving circuit for a final decoding stage of an EPROM, EEPROM or FLASH EPROM for battery powered apparatuses functioning at relatively low supply voltage avoids energy absorption from a commonly boosted voltage node by switching the capacitance of the control node of the p-channel pull-up device of the CMOS inverter that drives the memory line and which constitutes the load of the driving circuit. The node is effectively charged by drawing current from the supply node and is discharged rapidly by switching in parallel thereto a previously discharged capacitance. This charge-sharing switcheable capacitance may advantageously be the capacitance of a similar p-channel pull-up control node of a deselected wordline of the array.

摘要翻译： 用于在较低电源电压下工作的电池供电设备的EPROM，EEPROM或FLASH EPROM的最终解码级的驱动电路通过切换p沟道下拉单元的控制节点的电容来避免来自共同升压的电压节点的能量吸收， 该CMOS反相器驱动存储器线并构成驱动电路的负载。 该节点通过从电源节点引出电流被有效地充电，并且通过并联地切换预先放电的电容而迅速放电。 该电荷共享可切换电容可以有利地是阵列的未选择的字线的类似的p沟道上拉控制节点的电容。

公开(公告)号：US06477625B1

公开(公告)日：2002-11-05

申请号：US09474932

申请日：1999-12-29

申请人： Luigi Pascucci ,  Marco Fontana

发明人： Luigi Pascucci ,  Marco Fontana

IPC分类号： G06F1206

CPC分类号： G11C7/1018

摘要： A method for reading a memory by applying control signals. The control signals include a memory enable signal, a visibility signal, and a read signal. By applying the control signals to the memory, the memory is selectively configured into any of a plurality of cycles associated with reading the memory. The different cycles include: random read, pipeline-type random read, sequential read and suspend and wait cycles. Depending upon the cycle configuration of the memory, data is selectively emitted from the memory that coincides with the externally generated address.

摘要翻译： 一种通过应用控制信号读取存储器的方法。 控制信号包括存储器使能信号，可见度信号和读取信号。 通过将控制信号施加到存储器，存储器被选择性地配置成与读取存储器相关联的多个周期中的任一个。 不同的周期包括：随机读取，流水线型随机读取，顺序读取和挂起和等待周期。 根据存储器的周期配置，选择性地从存储器发射数据，这与外部产生的地址一致。

公开(公告)号：US5754483A

公开(公告)日：1998-05-19

申请号：US835033

申请日：1997-03-27

申请人： Luigi Pascucci ,  Paolo Rolandi ,  Marco Fontana ,  Antonio Barcella

发明人： Luigi Pascucci ,  Paolo Rolandi ,  Marco Fontana ,  Antonio Barcella

IPC分类号： G11C16/06 ,  G11C7/14 ,  G11C16/28 ,  G11C7/00

CPC分类号： G11C7/14 ,  G11C16/28

摘要： A reference word line and data propagation reproduction circuit, particularly for non-volatile memories provided with hierarchical decoders, where the memory is divided into at least two memory half-matrices that are arranged on different half-planes. The circuit includes, for each one of the at least two memory half-matrices, a reference unit for each one of the at least two memory half-matrices and an associated unit for reproducing the propagation of the signals along the reference unit. The reference unit and the associated propagation reproduction unit have a structure that is identical to each generic word line of the memory device. The reference and propagation reproduction units of one of the at least two memory half-matrices are activatable upon selection of a memory cell in the other one of the at least two memory half-matrices, in order to provide a reference that is synchronous and symmetrical with respect to the selection of the memory cell for reading it and so as to preset, according to the propagation reproduction unit conditions for starting correct and certain reading of the selected memory cell.

摘要翻译： 一种参考字线和数据传播再现电路，特别是用于提供有分层解码器的非易失性存储器，其中存储器被分成至少两个布置在不同半平面上的存储器半矩阵。 对于至少两个存储器半矩阵中的每一个，电路包括用于至少两个存储器半矩阵中的每一个的参考单元和用于再现信号沿着参考单元的传播的相关单元。 参考单元和相关联的传播再现单元具有与存储器件的每个通用字线相同的结构。 所述至少两个存储器半矩阵之一的参考和传播再现单元可以在选择所述至少两个存储器半矩阵中的另一个存储器半矩阵中的存储器单元时激活，以便提供同步和对称的参考 关于选择用于读取的存储单元，并且根据用于开始选择的存储单元的正确和特定读取的传播再现单元条件来预设存储单元。

公开(公告)号：US06148413A

公开(公告)日：2000-11-14

申请号：US835030

申请日：1997-03-28

申请人： Luigi Pascucci ,  Marco Fontana

发明人： Luigi Pascucci ,  Marco Fontana

IPC分类号： G11C5/02 ,  G11C16/28 ,  H02H3/05 ,  G11C29/00

CPC分类号： G11C16/28 ,  G11C5/025

摘要： Programming and reading management architecture, particularly for test purposes, for memory devices of the non-volatile type, comprising at least two memory half-matrices, a bidirectional internal bus for the transmission of data to and from the memory half-matrices, a programming unit for each one of the at least two memory half-matrices, and a data sensing unit. The programming units are adapted to program the at least two memory half-matrices and the data sensing unit and the programming units communicate with the bidirectional internal bus to reroute onto the bus reading data and programming data of the at least two memory half-matrices.

摘要翻译： 编程和读取管理架构，特别是用于测试目的，用于非易失性类型的存储器件，包括至少两个存储器半矩阵，用于向存储器半矩阵传输数据和从存储器半矩阵传输数据的双向内部总线，编程 所述至少两个存储器半矩阵中的每一个的单元，以及数据感测单元。 所述编程单元适于对所述至少两个存储器半矩阵进行编程，并且所述数据感测单元和所述编程单元与所述双向内部总线通信以重新路由到所述总线读取数据和所述至少两个存储器半矩阵的编程数据。

公开(公告)号：US5841728A

公开(公告)日：1998-11-24

申请号：US724495

申请日：1996-09-30

申请人： Luigi Pascucci ,  Paolo Rolandi ,  Marco Fontana ,  Antonio Barcella

发明人： Luigi Pascucci ,  Paolo Rolandi ,  Marco Fontana ,  Antonio Barcella

IPC分类号： G11C8/12 ,  G11C8/14 ,  G11C8/00

CPC分类号： G11C8/12 ,  G11C8/14

摘要： The memory device in accordance with the present invention has hierarchical row decoding architecture and comprises at least one main decoder and a plurality of secondary decoders. The decoders have outputs coupled to a plurality of word lines respectively through a plurality of auxiliary lines having first ends respectively connected to said outputs and second ends respectively connected to intermediate points of the word lines.

摘要翻译： 根据本发明的存储器件具有分级行解码架构，并且包括至少一个主解码器和多个辅助解码器。 解码器具有通过分别连接到分别连接到字线的中间点的所述输出和第二端的多个辅助线耦合到多个字线的输出。

公开(公告)号：US5821788A

公开(公告)日：1998-10-13

申请号：US790832

申请日：1997-01-30

申请人： Luigi Pascucci ,  Paolo Rolandi ,  Marco Fontana ,  Antonio Barcella

发明人： Luigi Pascucci ,  Paolo Rolandi ,  Marco Fontana ,  Antonio Barcella

IPC分类号： G11C5/14 ,  H03L7/00

CPC分类号： G11C5/143

摘要： A power-on-reset (P.O.R.) circuit produces a power-on-reset (P.O.R.) signal whose an amplitude tracks the voltage on a supply node until it exceeds a certain threshold. The circuit has a first monitoring and comparing circuit portion including at least a nonvolatile memory element having a control gate coupled to the supply node, a first current terminal coupled to a ground node, and a second current terminal coupled to a first node which is capacitively coupled to the supply node. The circuit further includes a second circuit portion that includes an intrinsically unbalanced bistable circuit, having a node that intrinsically is in a high state at power-on coupled to the first node that is intrinsically in a low state at power-on coupled to the input of an output buffer.

摘要翻译： 上电复位（P.O.R.）电路产生上电复位（P.O.R.）信号，其幅度跟踪供电节点上的电压，直到其超过某个阈值。 该电路具有第一监视和比较电路部分，该电路部分至少包括具有耦合到电源节点的控制栅极的非易失性存储器元件，耦合到接地节点的第一电流端子和耦合到电容性的第一节点的第二电流端子 耦合到供应节点。 该电路还包括第二电路部分，该第二电路部分包括本质上不平衡的双稳态电路，其具有在上电时本质上处于处于高状态的节点，所述节点在与所述输入端相连的上电时本质上处于处于低电平状态 的输出缓冲区。

公开(公告)号：US5659498A

公开(公告)日：1997-08-19

申请号：US684406

申请日：1996-07-19

申请人： Luigi Pascucci ,  Paolo Rolandi ,  Antonio Barcella ,  Marco Fontana

发明人： Luigi Pascucci ,  Paolo Rolandi ,  Antonio Barcella ,  Marco Fontana

IPC分类号： G06F11/20 ,  G11C7/20 ,  H03K3/356 ,  G11C11/00

CPC分类号： G11C7/20 ,  H03K3/356008 ,  H03K3/356104

摘要： A latch circuit that is intentionally unbalanced, so that a first output reaches ground voltage and a second output reaches a supply voltage. The latch circuit may be used with a fully static low-consumption fuse circuit which reverses the first and second outputs of the latch circuit when the fuse is in an unprogrammed state, but does not change the outputs of the latch circuit in the programmed state. In particular, the latch circuit has a first transistor of a first polarity series connected at a first output node with a second transistor of a second polarity between a supply voltage and a ground voltage. A third transistor of the first polarity is series connected at a second output node with a fourth transistor of the second polarity between the supply voltage and the ground voltage. The gate terminals of the first and second transistors are connected to the second output, while the gate terminals of the third and fourth transistors are connected to the first output. The first and third transistors have thresholds which are mutually different, and the second and fourth transistors have thresholds which are mutually different, so that the first output reaches ground voltage and the second output reaches the supply voltage. This circuit can be combined with a fuse circuit, such as a dual gate transistor.

摘要翻译： 有意不平衡的锁存电路，使得第一输出达到地电压，第二输出达到电源电压。 当熔断器处于未编程状态时，锁存电路可以与完全静态的低功耗熔丝电路一起使用，该电路使锁存电路的第一和第二输出反向，但在编程状态下不改变锁存电路的输出。 特别地，锁存电路具有第一极性串联的第一晶体管，在第一输出节点处连接有电源电压和接地电压之间的第二极性的第二晶体管。 第一极性的第三晶体管在第二输出节点处串联连接在电源电压和接地电压之间的第二极性的第四晶体管。 第一和第二晶体管的栅极端子连接到第二输出端，而第三和第四晶体管的栅极端子连接到第一输出端。 第一和第三晶体管具有相互不同的阈值，并且第二和第四晶体管具有相互不同的阈值，使得第一输出达到接地电压，第二输出达到电源电压。 该电路可以与诸如双栅极晶体管的熔丝电路组合。