公开(公告)号：US08367507B1

公开(公告)日：2013-02-05

申请号：US13404779

申请日：2012-02-24

申请人： Yoshinori Tsuchiya ,  Takashi Shinohe

发明人： Yoshinori Tsuchiya ,  Takashi Shinohe

IPC分类号： H01L21/336

CPC分类号： H01L29/7806 ,  H01L21/0485 ,  H01L29/0619 ,  H01L29/0834 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/47 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/868 ,  H01L29/872

摘要： A method for manufacturing a semiconductor device according to the present embodiment includes the steps of forming a metallic silicide film on an n-type impurity region and a p-type impurity region made of silicon carbide (SiC), performing ion implantation of phosphorous (P) into the metallic silicide film on the n-type impurity region, performing a first thermal treatment, performing ion implantation of aluminum (Al) into the metallic silicide film on the p-type impurity region, and performing a second thermal treatment at a temperature lower than the first thermal treatment.

摘要翻译： 根据本实施例的半导体器件的制造方法包括以下步骤：在n型杂质区上形成金属硅化物膜和由碳化硅（SiC）制成的p型杂质区，进行磷离子注入（P ）进入n型杂质区域的金属硅化物膜，进行第一热处理，对p型杂质区域的金属硅化物膜进行铝（Al）的离子注入，并进行第二次热处理 低于第一次热处理。

公开(公告)号：US07977210B2

公开(公告)日：2011-07-12

申请号：US12277749

申请日：2008-11-25

申请人： Chiharu Ota ,  Johji Nishio ,  Takashi Shinohe

发明人： Chiharu Ota ,  Johji Nishio ,  Takashi Shinohe

IPC分类号： H01L21/30

CPC分类号： H01L29/7802 ,  H01L24/83 ,  H01L29/0619 ,  H01L29/0878 ,  H01L29/1608 ,  H01L29/402 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/7395 ,  H01L29/872 ,  H01L2224/83001 ,  H01L2924/12036 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00

摘要： A semiconductor substrate includes a silicon carbide substrate having a first impurity concentration, a first silicon carbide layer formed on the silicon carbide substrate and having a second impurity concentration, and a second silicon carbide layer of a first conductivity type formed on the first silicon carbide layer and having a third impurity concentration, wherein the second impurity concentration is higher the an either the first impurity concentration or the third impurity concentration.

摘要翻译： 半导体衬底包括具有第一杂质浓度的碳化硅衬底，形成在碳化硅衬底上并具有第二杂质浓度的第一碳化硅层和形成在第一碳化硅层上的第一导电类型的第二碳化硅层 并且具有第三杂质浓度，其中第二杂质浓度高于第一杂质浓度或第三杂质浓度。

公开(公告)号：US20100078650A1

公开(公告)日：2010-04-01

申请号：US12407048

申请日：2009-03-19

申请人： Tetsuo Hatakeyama ,  Takashi Shinohe

发明人： Tetsuo Hatakeyama ,  Takashi Shinohe

IPC分类号： H01L29/24

CPC分类号： H01L29/7802 ,  H01L29/045 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1608

摘要： A semiconductor device includes a semiconductor substrate made of silicon carbide and having a surface, a normal vector for the surface having an off angle with respect to a direction or a direction, a semiconductor layer of a first conductivity type formed on the semiconductor substrate, a first semiconductor region of a second conductivity type formed in a surface region of the semiconductor layer, a source region of a first conductivity type formed in a surface region of the first semiconductor region, a second semiconductor region of a second conductivity type formed in the surface region of the semiconductor layer, contacting the first semiconductor region, and having a bottom surface lower than a bottom surface of the first semiconductor region, wherein at least one end of the bottom surface of the second semiconductor region is perpendicular to an off angle direction.

摘要翻译： 半导体器件包括由碳化硅制成并具有表面的半导体衬底，表面的法向矢量相对于<0001>方向或<000-1>方向具有偏离角，第一导电性的半导体层 形成在所述半导体衬底上的第一半导体区域，形成在所述半导体层的表面区域中的第二导电类型的第一半导体区域，形成在所述第一半导体区域的表面区域中的第一导电类型的源极区域， 形成在所述半导体层的表面区域中的第二导电类型，与所述第一半导体区域接触，并且具有低于所述第一半导体区域的底表面的底表面，其中所述第二半导体区域的底表面的至少一个端部 垂直于偏角方向。

公开(公告)号：US20090008650A1

公开(公告)日：2009-01-08

申请号：US12182816

申请日：2008-07-30

申请人： Makoto MIZUKAMI ,  Takashi Shinohe

发明人： Makoto MIZUKAMI ,  Takashi Shinohe

IPC分类号： H01L29/24

CPC分类号： H01L29/7802 ,  H01L29/0619 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/167 ,  H01L29/66068 ,  H01L29/7392 ,  H01L29/7828 ,  H01L29/8083

摘要： A decrease in breakdown voltage can be prevented as much as possible. A field-effect transistor includes: a drain region made of SiC; a drift layer which is formed on the drain region and is made of n-type SiC; a source region which is formed on the surface of the drift layer and is made of n-type SiC; a channel region which is formed on the surface of the drift layer located on a side of the source region and is made of SiC; an insulating gate which is formed on the channel region; and a p-type base region interposed between the bottom portion of the source region and the drift region, and containing two kinds of p-type impurities.

摘要翻译： 可以尽可能地防止击穿电压的降低。 场效应晶体管包括：由SiC制成的漏区; 漂移层，其形成在漏区，由n型SiC制成; 源区，其形成在漂移层的表面上并由n型SiC制成; 沟道区，形成在位于源极区一侧的漂移层的表面上并由SiC制成; 形成在沟道区上的绝缘栅; 以及插入在源极区域的底部与漂移区域之间的p型基极区域，并且含有两种p型杂质。

公开(公告)号：US20080169475A1

公开(公告)日：2008-07-17

申请号：US11827553

申请日：2007-07-12

申请人： Johji Nishio ,  Takuma Suzuki ,  Chiharu Ota ,  Takashi Shinohe

发明人： Johji Nishio ,  Takuma Suzuki ,  Chiharu Ota ,  Takashi Shinohe

IPC分类号： H01L29/24 ,  H01L29/872

CPC分类号： H01L29/872 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/1608

摘要： A semiconductor device includes a first-conductivity-type SiC substrate, a first-conductivity-type SiC semiconductor layer formed on the substrate, whose impurity concentration is lower than that of the substrate, a first electrode formed on the semiconductor layer and forming a Schottky junction with the semiconductor layer, a barrier height of the Schottky junction being 1 eV or less, plural second-conductivity-type junction barriers formed to contact the first electrode and each having a depth d1 from an upper surface of the semiconductor layer, a width w, and a space s between adjacent ones of the junction barriers, a second-conductivity-type edge termination region formed outside the junction barriers to contact the first electrode and having a depth d2 from the upper surface of the semiconductor layer, and a second electrode formed on the second surface of the substrate, wherein following relations are satisfied d1/d2≧1, s/d1≦0.6, and s/(w+s)≦0.33.

摘要翻译： 半导体器件包括第一导电型SiC衬底，在衬底上形成的杂质浓度低于衬底的第一导电型SiC半导体层，形成在半导体层上并形成肖特基 与所述半导体层的接合，所述肖特基结的势垒高度为1eV以下，形成为与所述第一电极接触并且各自具有来自所述半导体层的上表面的深度d 1的多个第二导电型接合阻挡层， 宽度w和相邻接合屏障之间的空间s，形成在接合屏障外部的第二导电类型边缘终端区域，以接触第一电极并且具有距离半导体层的上表面的深度d 2;以及 形成在基板的第二表面上的第二电极，其中满足以下关系：d 1 / d 2> = 1，s / d 1 <= 0.6，以及s /（w + s）<= 0.33。

公开(公告)号：US20070045764A1

公开(公告)日：2007-03-01

申请号：US11505809

申请日：2006-08-18

申请人： Tetsuo Hatakeyama ,  Takashi Shinohe

发明人： Tetsuo Hatakeyama ,  Takashi Shinohe

IPC分类号： H01L31/07

CPC分类号： H01L29/872 ,  H01L29/0615 ,  H01L29/08

摘要： A semiconductor device includes a semiconductor substrate of a first conductivity type, a semiconductor region of the first conductivity type formed on a top surface of the semiconductor substrate, a lower electrode formed on a bottom surface of the semiconductor substrate, an upper electrode formed on a top surface of the semiconductor region, a buried semiconductor layer of a second conductivity type formed in the semiconductor region, a first semiconductor layer of the second conductivity type, formed on the top surface of the semiconductor region and connected to the upper electrode, and a second semiconductor layer of the second conductivity type, formed on a side surface of the semiconductor region and connected to the buried semiconductor layer and the first semiconductor layer, the second semiconductor layer having a lower second conductivity type impurity concentration than the buried semiconductor layer.

摘要翻译： 半导体器件包括第一导电类型的半导体衬底，形成在半导体衬底的顶表面上的第一导电类型的半导体区域，形成在半导体衬底的底表面上的下电极，形成在半导体衬底的上表面上的上电极 半导体区域的顶表面，形成在半导体区域中的第二导电类型的掩埋半导体层，形成在半导体区域的顶表面上并连接到上电极的第二导电类型的第一半导体层，以及 第二导电类型的第二半导体层形成在半导体区域的侧表面上并连接到掩埋半导体层和第一半导体层，第二半导体层具有比掩埋半导体层低的第二导电类型杂质浓度。

公开(公告)号：US20070023781A1

公开(公告)日：2007-02-01

申请号：US11493832

申请日：2006-07-27

申请人： Makoto Mizukami ,  Takashi Shinohe

发明人： Makoto Mizukami ,  Takashi Shinohe

IPC分类号： H01L31/00

CPC分类号： H01L29/872 ,  H01L29/1608 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/8611

摘要： A semiconductor rectifier has a semiconductor layer formed on a substrate, an electric field reduced layer of conductive type contrary to that of the semiconductor layer, which is formed on the semiconductor layer positioned on a bottom portion of a trench formed on a portion of the semiconductor layer, a first electrode connected on the semiconductor layer adjacent to the trench by Schottky junction, a second electrode which is connected on sidewalls of the trench by Schottky junction, electrically conductive with the first electrode and made of a material different from that of the first electrode, and a third electrode formed on the substrate at opposite side of the semiconductor layer.

摘要翻译： 半导体整流器具有形成在基板上的半导体层，与半导体层相反的导电类型的电场降低层形成在位于形成在半导体的一部分上的沟槽的底部上的半导体层上 层，通过肖特基结连接在与沟槽相邻的半导体层上的第一电极，通过肖特基结连接在沟槽的侧壁上的第二电极，与第一电极导电并且由不同于第一电极的材料制成 电极，以及在半导体层的相对侧的基板上形成的第三电极。

公开(公告)号：US07049675B2

公开(公告)日：2006-05-23

申请号：US10795270

申请日：2004-03-09

申请人： Kozo Kinoshita ,  Tetsuo Hatakeyama ,  Takashi Shinohe

发明人： Kozo Kinoshita ,  Tetsuo Hatakeyama ,  Takashi Shinohe

IPC分类号： H01L23/58

CPC分类号： H01L29/7811 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/402 ,  H01L29/404 ,  H01L29/66143 ,  H01L29/7813 ,  H01L29/872 ,  H01L2924/0002 ,  H01L2924/00

摘要： A high withstand voltage semiconductor device does not show any significant fall of its withstand voltage if the impurity concentration of the RESURF layer of a low impurity concentration semiconductor region thereof varies from the optimal level and/or influenced by the fixed electric charge. The device is produced by forming a ring-shaped high impurity concentration edge termination layer of a second conductivity type and a ring-shaped low impurity concentration RESURF layer of the second conductivity type on the front surface of a semiconductor layer of a first conductivity type carrying electrodes respectively on the opposite surfaces thereof along the outer edge of one of the electrodes, then forming an outer ring layer with an impurity concentration substantially as low as the RESURF layer concentrically outside the RESURF layer with a gap separating therebetween and subsequently forming an inner ring layer with an impurity concentration substantially as high as the edge termination layer concentrically inside the RESURF layer.

公开(公告)号：US20060102908A1

公开(公告)日：2006-05-18

申请号：US11272858

申请日：2005-11-15

申请人： Seiji Imai ,  Takashi Shinohe

发明人： Seiji Imai ,  Takashi Shinohe

IPC分类号： H01L31/0312

CPC分类号： H01L29/7802 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7813 ,  H01L29/7816

摘要： A semiconductor device includes an SiC substrate, an SiC layer of a first conductivity type disposed on the upper surface of the SiC substrate, a first SiC region of a second conductivity type disposed on the SiC layer, a second SiC region of the first conductivity type disposed on a surface region of the first SiC region, including a nitrogen-added first sub-region and a phosphorus-added second sub-region disposed in contact with the first sub-region, a gate insulating film disposed to extend over the SiC layer, first SiC region, and first sub-region of the second SiC region, a gate electrode formed on the gate insulating film, a first electrode formed on the second sub-region of the second SiC region and the first SiC region, and a second electrode formed on the lower surface of the SiC substrate.

摘要翻译： 半导体器件包括SiC衬底，设置在SiC衬底的上表面上的第一导电类型的SiC层，设置在SiC层上的第二导电类型的第一SiC区域，第一导电类型的第二SiC区域 设置在与所述第一子区域接触的包括添加氮的第一子区域和添加磷的第二子区域的所述第一SiC区域的表面区域上，设置成在所述SiC层上延伸的栅极绝缘膜 第一SiC区域和第二SiC区域的第一子区域，形成在栅极绝缘膜上的栅电极，形成在第二SiC区域的第二子区域上的第一电极和第一SiC区域，以及第二SiC区域 形成在SiC衬底的下表面上的电极。

公开(公告)号：US20050029558A1

公开(公告)日：2005-02-10

申请号：US10942000

申请日：2004-09-16

申请人： Tetsuo Hatakeyama ,  Takashi Shinohe

发明人： Tetsuo Hatakeyama ,  Takashi Shinohe

IPC分类号： H01L29/06 ,  H01L29/10 ,  H01L29/24 ,  H01L29/739 ,  H01L29/772 ,  H01L29/78 ,  H01L31/112

CPC分类号： H01L29/7811 ,  H01L29/0615 ,  H01L29/0661 ,  H01L29/0692 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7392 ,  H01L29/7395 ,  H01L29/7722 ,  H01L29/7802 ,  H01L29/872

摘要： A high-breakdown-voltage semiconductor device comprises a high-resistance semiconductor layer, trenches formed on the surface thereof in a longitudinal plane shape and in parallel, first regions formed on the semiconductor layer to be sandwiched between adjacent ones of the trenches and having an impurity concentration higher than that of the semiconductor layer, a second region having opposite conductivity to the first regions and continuously disposed in a trench sidewall and bottom portion, a sidewall insulating film disposed on the second region of the trench sidewall, a third region disposed on the second region of the trench bottom portion and having the same conductivity as and the higher impurity concentration than the second region, a fourth region disposed on the back surface of the semiconductor layer, a first electrode formed on each first region, a second electrode connected to the third region, and a third electrode formed on the fourth region.