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公开(公告)号：US09029869B2
公开(公告)日：2015-05-12
申请号：US13034264
申请日：2011-02-24
申请人： Hiroshi Kono , Takashi Shinohe , Chiharu Ota , Makoto Mizukami , Takuma Suzuki , Johji Nishio
发明人： Hiroshi Kono , Takashi Shinohe , Chiharu Ota , Makoto Mizukami , Takuma Suzuki , Johji Nishio
IPC分类号： H01L29/15 , H01L29/739 , H01L29/10 , H01L29/66
CPC分类号： H01L29/7395 , H01L29/1033 , H01L29/66333
摘要： One embodiment of a semiconductor device includes: a silicon carbide substrate including first and second principal surfaces; a first-conductive-type silicon carbide layer on the first principal surface; a second-conductive-type first silicon carbide region at a surface of the first silicon carbide layer; a first-conductive-type second silicon carbide region at the surface of the first silicon carbide region; a second-conductive-type third silicon carbide region at the surface of the first silicon carbide region; a second-conductive-type fourth silicon carbide region formed between the first silicon carbide region and the second silicon carbide region, and having an impurity concentration higher than that of the first silicon carbide region; a gate insulator; a gate electrode formed on the gate insulator; an inter-layer insulator; a first electrode connected to the second silicon carbide region and the third silicon carbide region; and a second electrode on the second principal surface.
摘要翻译： 半导体器件的一个实施例包括：包含第一和第二主表面的碳化硅衬底; 第一主表面上的第一导电型碳化硅层; 在所述第一碳化硅层的表面处的第二导电型第一碳化硅区域; 在第一碳化硅区域的表面处的第一导电型第二碳化硅区域; 在第一碳化硅区域的表面处的第二导电型第三碳化硅区域; 在第一碳化硅区域和第二碳化硅区域之间形成的杂质浓度高于第一碳化硅区域的第二导电型第四碳化硅区域; 栅极绝缘体; 形成在栅极绝缘体上的栅电极; 层间绝缘体; 连接到所述第二碳化硅区域和所述第三碳化硅区域的第一电极; 和在第二主表面上的第二电极。
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公开(公告)号：US08569795B2
公开(公告)日：2013-10-29
申请号：US13217472
申请日：2011-08-25
CPC分类号： H01L29/7802 , H01L21/049 , H01L29/0623 , H01L29/1608 , H01L29/4236 , H01L29/45 , H01L29/4966 , H01L29/66068 , H01L29/7813
摘要： A semiconductor device of an embodiment includes: a silicon carbide substrate including first and second principal surfaces; a first conductive-type first silicon carbide layer provided on the first principal surface of the silicon carbide substrate; a second conductive-type first silicon carbide region formed on a surface of the first silicon carbide layer; a first conductive-type second silicon carbide region formed on a surface of the first silicon carbide region; a second conductive-type third silicon carbide region formed on the surface of the first silicon carbide region; a gate insulating film continuously formed on the surfaces of the first silicon carbide layer, the first silicon carbide region, and the second silicon carbide region; a first electrode formed of silicon carbide formed on the gate insulating film; a second electrode formed on the first electrode; an interlayer insulating film for covering the first and second electrodes; a third electrode electrically connected to the second silicon carbide region and the third silicon carbide region; and a fourth electrode formed on the second principal surface of the silicon carbide substrate.
摘要翻译： 实施例的半导体器件包括：碳化硅衬底，其包括第一和第二主表面; 设置在碳化硅衬底的第一主表面上的第一导电型第一碳化硅层; 形成在所述第一碳化硅层的表面上的第二导电型第一碳化硅区; 形成在所述第一碳化硅区域的表面上的第一导电型第二碳化硅区域; 形成在所述第一碳化硅区域的表面上的第二导电型第三碳化硅区域; 连续形成在所述第一碳化硅层，所述第一碳化硅区域和所述第二碳化硅区域的表面上的栅极绝缘膜; 形成在所述栅极绝缘膜上的由碳化硅形成的第一电极; 形成在第一电极上的第二电极; 用于覆盖第一和第二电极的层间绝缘膜; 电连接到第二碳化硅区域和第三碳化硅区域的第三电极; 以及形成在碳化硅衬底的第二主表面上的第四电极。
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公开(公告)号：US07368783B2
公开(公告)日：2008-05-06
申请号：US11230492
申请日：2005-09-21
申请人： Makoto Mizukami , Takashi Shinohe
发明人： Makoto Mizukami , Takashi Shinohe
IPC分类号： H01L29/94
CPC分类号： H01L29/7813 , H01L29/0623 , H01L29/0634 , H01L29/086 , H01L29/0878 , H01L29/66666 , H01L29/7397 , H01L29/7811 , H01L29/7828 , H01L29/8083
摘要： A semiconductor device includes a semiconductor substrate of a first conductivity type, a lightly-doped semiconductor layer of the first conductivity type formed on the first major surface of the substrate, a first semiconductor region of the first conductivity type formed on an island-shaped region on the lightly-doped semiconductor layer, a first electrode surrounding the first semiconductor region and buried at a deeper position than the first semiconductor region, a second semiconductor region formed on the second major surface of the substrate, a buried field relaxation layer formed in the lightly-doped semiconductor layer between a bottom surface of the first electrode and the second semiconductor region, including a first field relaxation layer of the first conductivity type and second field relaxation layers of the second conductivity type formed at two ends of the first field relaxation layer, second and third electrodes formed on the first and second semiconductor regions, respectively.
摘要翻译： 半导体器件包括第一导电类型的半导体衬底，形成在衬底的第一主表面上的第一导电类型的轻掺杂半导体层，形成在岛状区域上的第一导电类型的第一半导体区域 在所述轻掺杂半导体层上，包围所述第一半导体区并且埋藏在比所述第一半导体区更深的位置的第一电极，形成在所述衬底的所述第二主表面上的第二半导体区， 在第一电极的底表面和第二半导体区域之间的轻掺杂半导体层，包括第一导电类型的第一场弛豫层和形成在第一场弛豫层两端的第二导电类型的第二场弛豫层 ，形成在第一和第二半导体区域上的第二和第三电极， 分别。
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公开(公告)号：US20120228734A1
公开(公告)日：2012-09-13
申请号：US13226883
申请日：2011-09-07
申请人： Masamu KAMAGA , Makoto Mizukami , Takashi Shinohe
发明人： Masamu KAMAGA , Makoto Mizukami , Takashi Shinohe
IPC分类号： H01L29/861 , H01L21/20
CPC分类号： H01L29/0615 , H01L29/0692 , H01L29/6609 , H01L29/8613
摘要： A high breakdown voltage diode of the present embodiment includes a first conductive semiconductor substrate, a drift layer formed on the first conductive semiconductor substrate and formed of a first conductive semiconductor, a buffer layer formed on the drift layer and formed of a second conductive semiconductor, a second conductive high concentration semiconductor region formed at an upper portion of the buffer layer, a mesa termination unit formed on an end region of a semiconductor apparatus to relax an electric field of the end region when reverse bias is applied between the semiconductor substrate and the buffer layer, and an electric field relaxation region formed at the mesa termination unit and formed of a second conductive semiconductor.A breakdown voltage of a high breakdown voltage diode, in which a pn junction is provided to a semiconductor layer, is increased, and a process yield is improved.
摘要翻译： 本实施例的高击穿电压二极管包括第一导电半导体衬底，形成在第一导电半导体衬底上并由第一导电半导体形成的漂移层，形成在漂移层上并由第二导电半导体形成的缓冲层， 形成在缓冲层的上部的第二导电性高浓度半导体区域，形成在半导体装置的端部区域上的台面终端单元，用于在半导体基板与半导体基板之间施加反向偏压时使末端区域的电场松弛 缓冲层和形成在台面终端单元处并由第二导电半导体形成的电场弛豫区域。 提供了将pn结提供给半导体层的高击穿电压二极管的击穿电压，并且提高了工艺成品率。
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公开(公告)号：US08012837B2
公开(公告)日：2011-09-06
申请号：US12716403
申请日：2010-03-03
申请人： Johji Nishio , Chiharu Ota , Takuma Suzuki , Hiroshi Kono , Makoto Mizukami , Takashi Shinohe
发明人： Johji Nishio , Chiharu Ota , Takuma Suzuki , Hiroshi Kono , Makoto Mizukami , Takashi Shinohe
IPC分类号： H01L21/336 , H01L21/425 , H01L21/265
CPC分类号： H01L29/7802 , H01L21/02378 , H01L21/02433 , H01L21/02529 , H01L21/02658 , H01L21/0495 , H01L21/30604 , H01L29/0878 , H01L29/1608 , H01L29/66068 , H01L29/66143 , H01L29/872 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a semiconductor device capable of realizing a high yield of a large-scale semiconductor device even when a silicon carbide semiconductor including a defect is used is provided. The method of manufacturing a semiconductor device includes: a step of epitaxially growing a silicon carbide semiconductor layer on a silicon carbide semiconductor substrate; a step of polishing a surface of the silicon carbide semiconductor layer; a step of ion-implanting impurities into the silicon carbide semiconductor layer after the step of polishing; a step of performing heat treatment to activate the impurities; a step of forming a first thermal oxide film on the surface of the silicon carbide semiconductor layer after the step of performing heat treatment; a step of chemically removing the first thermal oxide film; and a step of forming an electrode layer on the silicon carbide semiconductor film.
摘要翻译： 提供了即使当使用包括缺陷的碳化硅半导体时也能够实现大规模半导体器件的高产率的半导体器件的制造方法。 制造半导体器件的方法包括：在碳化硅半导体衬底上外延生长碳化硅半导体层的步骤; 抛光所述碳化硅半导体层的表面的步骤; 在抛光步骤之后将杂质离子注入到碳化硅半导体层中的步骤; 进行热处理以活化杂质的步骤; 在进行热处理的步骤之后，在碳化硅半导体层的表面上形成第一热氧化膜的工序; 化学去除第一热氧化膜的步骤; 以及在所述碳化硅半导体膜上形成电极层的步骤。
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公开(公告)号：US20060011973A1
公开(公告)日：2006-01-19
申请号：US11230492
申请日：2005-09-21
申请人： Makoto Mizukami , Takashi Shinohe
发明人： Makoto Mizukami , Takashi Shinohe
IPC分类号： H01L29/94
CPC分类号： H01L29/7813 , H01L29/0623 , H01L29/0634 , H01L29/086 , H01L29/0878 , H01L29/66666 , H01L29/7397 , H01L29/7811 , H01L29/7828 , H01L29/8083
摘要： A semiconductor device includes a semiconductor substrate of a first conductivity type, a lightly-doped semiconductor layer of the first conductivity type formed on the first major surface of the substrate, a first semiconductor region of the first conductivity type formed on an island-shaped region on the lightly-doped semiconductor layer, a first electrode surrounding the first semiconductor region and buried at a deeper position than the first semiconductor region, a second semiconductor region formed on the second major surface of the substrate, a buried field relaxation layer formed in the lightly-doped semiconductor layer between a bottom surface of the first electrode and the second semiconductor region, including a first field relaxation layer of the first conductivity type and second field relaxation layers of the second conductivity type formed at two ends of the first field relaxation layer, second and third electrodes formed on the first and second semiconductor regions, respectively.
摘要翻译： 半导体器件包括第一导电类型的半导体衬底，形成在衬底的第一主表面上的第一导电类型的轻掺杂半导体层，形成在岛状区域上的第一导电类型的第一半导体区域 在所述轻掺杂半导体层上，包围所述第一半导体区并且埋藏在比所述第一半导体区更深的位置的第一电极，形成在所述衬底的所述第二主表面上的第二半导体区， 在第一电极的底表面和第二半导体区域之间的轻掺杂半导体层，包括第一导电类型的第一场弛豫层和形成在第一场弛豫层两端的第二导电类型的第二场弛豫层 ，形成在第一和第二半导体区域上的第二和第三电极， 分别。
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公开(公告)号：US06969887B2
公开(公告)日：2005-11-29
申请号：US11038043
申请日：2005-01-21
申请人： Makoto Mizukami , Takashi Shinohe
发明人： Makoto Mizukami , Takashi Shinohe
IPC分类号： H01L29/78 , H01L21/336 , H01L29/06 , H01L29/08 , H01L29/24 , H01L29/739 , H01L29/808 , H01L29/94 , H01L31/062
CPC分类号： H01L29/7813 , H01L29/0623 , H01L29/0634 , H01L29/086 , H01L29/0878 , H01L29/66666 , H01L29/7397 , H01L29/7811 , H01L29/7828 , H01L29/8083
摘要： A semiconductor device includes a semiconductor substrate of a first conductivity type, a lightly-doped semiconductor layer of the first conductivity type formed on the first major surface of the substrate, a first semiconductor region of the first conductivity type formed on an island-shaped region on the lightly-doped semiconductor layer, a first electrode surrounding the first semiconductor region and buried at a deeper position than the first semiconductor region, a second semiconductor region formed on the second major surface of the substrate, a buried field relaxation layer formed in the lightly-doped semiconductor layer between a bottom surface of the first electrode and the second semiconductor region, including a first field relaxation layer of the first conductivity type and second field relaxation layers of the second conductivity type formed at two ends of the first field relaxation layer, second and third electrodes formed on the first and second semiconductor regions, respectively.
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公开(公告)号：US20050161732A1
公开(公告)日：2005-07-28
申请号：US11038043
申请日：2005-01-21
申请人： Makoto Mizukami , Takashi Shinohe
发明人： Makoto Mizukami , Takashi Shinohe
IPC分类号： H01L29/78 , H01L21/336 , H01L29/06 , H01L29/08 , H01L29/24 , H01L29/739 , H01L29/808 , H01L29/94 , H01L31/062
CPC分类号： H01L29/7813 , H01L29/0623 , H01L29/0634 , H01L29/086 , H01L29/0878 , H01L29/66666 , H01L29/7397 , H01L29/7811 , H01L29/7828 , H01L29/8083
摘要： A semiconductor device includes a semiconductor substrate of a first conductivity type, a lightly-doped semiconductor layer of the first conductivity type formed on the first major surface of the substrate, a first semiconductor region of the first conductivity type formed on an island-shaped region on the lightly-doped semiconductor layer, a first electrode surrounding the first semiconductor region and buried at a deeper position than the first semiconductor region, a second semiconductor region formed on the second major surface of the substrate, a buried field relaxation layer formed in the lightly-doped semiconductor layer between a bottom surface of the first electrode and the second semiconductor region, including a first field relaxation layer of the first conductivity type and second field relaxation layers of the second conductivity type formed at two ends of the first field relaxation layer, second and third electrodes formed on the first and second semiconductor regions, respectively.
摘要翻译： 半导体器件包括第一导电类型的半导体衬底，形成在衬底的第一主表面上的第一导电类型的轻掺杂半导体层，形成在岛状区域上的第一导电类型的第一半导体区域 在所述轻掺杂半导体层上，包围所述第一半导体区并且埋藏在比所述第一半导体区更深的位置的第一电极，形成在所述衬底的所述第二主表面上的第二半导体区， 在第一电极的底表面和第二半导体区域之间的轻掺杂半导体层，包括第一导电类型的第一场弛豫层和形成在第一场弛豫层两端的第二导电类型的第二场弛豫层 ，形成在第一和第二半导体区域上的第二和第三电极， 分别。
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公开(公告)号：US08987812B2
公开(公告)日：2015-03-24
申请号：US13203341
申请日：2010-01-06
申请人： Hiroshi Kono , Takashi Shinohe , Makoto Mizukami
发明人： Hiroshi Kono , Takashi Shinohe , Makoto Mizukami
IPC分类号： H01L29/66 , H01L29/739 , H01L21/04 , H01L29/417 , H01L29/45 , H01L29/78 , H01L29/16 , H01L29/423
CPC分类号： H01L29/7802 , H01L21/0465 , H01L21/0485 , H01L29/1608 , H01L29/41766 , H01L29/42368 , H01L29/45 , H01L29/66068 , H01L29/66325 , H01L29/66477 , H01L29/7393 , H01L29/7396 , H01L29/7397 , H01L29/78 , H01L29/7813
摘要： The invention provides an ultra-low-on-resistance, excellent-reliability semiconductor device that can finely be processed using SiC and a semiconductor device producing method. A semiconductor device includes: a silicon carbide substrate; a first-conductive-type first silicon carbide layer provided on a first principal surface of the silicon carbide substrate; a second-conductive-type first silicon carbide region formed at a surface of the first silicon carbide layer; a first-conductive-type second silicon carbide region formed at a surface of the first silicon carbide region; a second-conductive-type third silicon carbide region formed below the second silicon carbide region; a trench piercing through the second silicon carbide region to reach the third silicon carbide region; a gate insulating film; a gate electrode; an interlayer insulating film with which the gate electrode is covered; a first electrode that is formed on the second silicon carbide region and the interlayer insulating film in a side surface of the trench while containing a metallic element selected from a group consisting of Ni, Ti, Ta, Mo, and W; a second electrode that is formed on the third silicon carbide region in a bottom portion of the trench and the first electrode while containing Al; a first main electrode formed on the second electrode; and a second main electrode formed on a second principal surface of the silicon carbide substrate.
摘要翻译： 本发明提供可以使用SiC和半导体器件制造方法精细加工的超低导通电阻，优异可靠性的半导体器件。 半导体器件包括：碳化硅衬底; 设置在所述碳化硅衬底的第一主表面上的第一导电型第一碳化硅层; 形成在所述第一碳化硅层的表面的第二导电型第一碳化硅区; 形成在所述第一碳化硅区域的表面处的第一导电型第二碳化硅区域; 形成在所述第二碳化硅区域下方的第二导电型第三碳化硅区域; 穿过所述第二碳化硅区域的沟槽到达所述第三碳化硅区域; 栅极绝缘膜; 栅电极; 覆盖栅电极的层间绝缘膜; 形成在第二碳化硅区域上的第一电极和沟槽侧表面中的层间绝缘膜，同时含有选自Ni，Ti，Ta，Mo和W的金属元素; 第二电极，其形成在所述沟槽的底部中的所述第三碳化硅区域和所述第一电极同时含有Al; 形成在第二电极上的第一主电极; 以及形成在所述碳化硅衬底的第二主表面上的第二主电极。
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公开(公告)号：US20120037922A1
公开(公告)日：2012-02-16
申请号：US13203341
申请日：2010-01-06
申请人： Hiroshi Kono , Takashi Shinohe , Makoto Mizukami
发明人： Hiroshi Kono , Takashi Shinohe , Makoto Mizukami
IPC分类号： H01L29/161 , H01L21/331
CPC分类号： H01L29/7802 , H01L21/0465 , H01L21/0485 , H01L29/1608 , H01L29/41766 , H01L29/42368 , H01L29/45 , H01L29/66068 , H01L29/66325 , H01L29/66477 , H01L29/7393 , H01L29/7396 , H01L29/7397 , H01L29/78 , H01L29/7813
摘要： The invention provides an ultra-low-on-resistance, excellent-reliability semiconductor device that can finely be processed using SiC and a semiconductor device producing method. A semiconductor device includes: a silicon carbide substrate; a first-conductive-type first silicon carbide layer provided on a first principal surface of the silicon carbide substrate; a second-conductive-type first silicon carbide region formed at a surface of the first silicon carbide layer; a first-conductive-type second silicon carbide region formed at a surface of the first silicon carbide region; a second-conductive-type third silicon carbide region formed below the second silicon carbide region; a trench piercing through the second silicon carbide region to reach the third silicon carbide region; a gate insulating film; a gate electrode; an interlayer insulating film with which the gate electrode is covered; a first electrode that is formed on the second silicon carbide region and the interlayer insulating film in a side surface of the trench while containing a metallic element selected from a group consisting of Ni, Ti, Ta, Mo, and W; a second electrode that is formed on the third silicon carbide region in a bottom portion of the trench and the first electrode while containing Al; a first main electrode formed on the second electrode; and a second main electrode formed on a second principal surface of the silicon carbide substrate.
摘要翻译： 本发明提供可以使用SiC和半导体器件制造方法精细加工的超低导通电阻，优异可靠性的半导体器件。 半导体器件包括：碳化硅衬底; 设置在所述碳化硅衬底的第一主表面上的第一导电型第一碳化硅层; 形成在所述第一碳化硅层的表面的第二导电型第一碳化硅区; 形成在所述第一碳化硅区域的表面处的第一导电型第二碳化硅区域; 形成在所述第二碳化硅区域下方的第二导电型第三碳化硅区域; 穿过所述第二碳化硅区域的沟槽到达所述第三碳化硅区域; 栅极绝缘膜; 栅电极; 覆盖栅电极的层间绝缘膜; 形成在第二碳化硅区域上的第一电极和沟槽侧表面中的层间绝缘膜，同时含有选自Ni，Ti，Ta，Mo和W的金属元素; 第二电极，其形成在所述沟槽的底部中的所述第三碳化硅区域和所述第一电极同时含有Al; 形成在第二电极上的第一主电极; 以及形成在所述碳化硅衬底的第二主表面上的第二主电极。
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