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公开(公告)号：US20210247936A1
公开(公告)日：2021-08-12
申请号：US17240723
申请日：2021-04-26
Applicant: Micron Technology, Inc.
Inventor： Nadav Grosz , David Aaron Palmer
IPC: G06F3/06
Abstract: Devices and techniques for an adjustable watchdog in a memory device are disclosed herein. A memory operation command is received at a first time with a memory device from a host. A reset signal is received, with the memory device from the host, at a second time following the first time. A time interval between the first time and the second time is measured. A delay interval for a timer in the memory device to reset the memory device independently of receiving a further reset signal from the host is established based on the measured time interval.
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公开(公告)号：US20210200631A1
公开(公告)日：2021-07-01
申请号：US17014771
申请日：2020-09-08
Applicant: Micron Technology, Inc.
Inventor： David Aaron Palmer , Nadav Grosz , Lance W. Dover , Yoav Weinberg
Abstract: A storage device includes a memory storage region and a controller having a processor. The processor retrieves user data from the memory storage region using a physical block address corresponding to a logical block address (LBA), in response to a read command. The retrieved user data includes a first hash received through a host interface in a prior host data transmission. The processor further performs error correction on the user data to generate error-corrected user data. The processor further causes a cryptographic engine to produce a second hash of the error-corrected user data. The first hash is compared to the second hash associated with the error-corrected user data to determine a match result. A notification is generated in response to the match result.
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公开(公告)号：US20210141570A1
公开(公告)日：2021-05-13
申请号：US17157539
申请日：2021-01-25
Applicant: Micron Technology, Inc.
Inventor： Nadav Grosz , David Aaron Palmer
IPC: G06F3/06
Abstract: Devices and techniques for host adaptive memory device optimization are provided. A memory device can maintain a host model of interactions with a host. A set of commands from the host can be evaluated to create a profile of the set of commands. The profile can be compared to the host model to determine an inconsistency between the profile and the host model. An operation of the memory device can then be modified based on the inconsistency.
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公开(公告)号：US10997071B2
公开(公告)日：2021-05-04
申请号：US16201537
申请日：2018-11-27
Applicant: Micron Technology, Inc.
Inventor： David Aaron Palmer
IPC: G06F12/0804
Abstract: Devices and techniques for enhanced flush transfer efficiency in a storage device are described herein. A flush trigger for a user data write can be identified. Here, user data corresponds to the user data write and was stored in a buffer. The size of the user data stored in the buffer is smaller than a write width for a storage device subject to the write. The difference ins the user data size in the buffer and the write width is buffer free space. Additional data can be marshalled in response to the identification of the flush trigger. Here, the additional data size is less than or equal to the buffer free space. The user data and the additional data can then be written to the storage device.
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公开(公告)号：US10991436B2
公开(公告)日：2021-04-27
申请号：US16894397
申请日：2020-06-05
Applicant: Micron Technology, Inc.
Inventor： David Aaron Palmer
Abstract: Disclosed in some examples are methods, systems, memory devices, and machine-readable mediums which increase read throughput by introducing a delay prior to issuing a command to increase the chances that read commands can be executed in parallel. Upon receipt of a read command, if there are no other read commands in the command queue for a given portion (e.g., plane or plane group) of the die, the controller can delay issuing the read command for a delay period using a timer. If, during the delay period, an eligible read command is received, the delayed command and the newly received command are both issued in parallel using a multi-plane read. If no eligible read command is received during the delay period, the read command is issued after the delay period expires.
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Patent Agency Ranking
公开(公告)号：US10990319B2
公开(公告)日：2021-04-27
申请号：US16010940
申请日：2018-06-18
Applicant: Micron Technology, Inc.
Inventor： Nadav Grosz , David Aaron Palmer
Abstract: Devices and techniques for an adjustable watchdog in a memory device are disclosed herein. A memory operation command is received at a first time with a memory device from a host. A reset signal is received, with the memory device from the host, at a second time following the first time. A time interval between the first time and the second time is measured. A delay interval for a timer in the memory device to reset the memory device independently of receiving a further reset signal from the host is established based on the measured time interval.
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公开(公告)号：US20210109666A1
公开(公告)日：2021-04-15
申请号：US17129087
申请日：2020-12-21
Applicant: Micron Technology, Inc.
Inventor： David Aaron Palmer , Sean L. Manion , Jonathan Scott Parry , Stephen Hanna , Qing Liang , Nadav Grosz , Christian M. Gyllenskog , Kulachet Tanpairoj
Abstract: Apparatus and methods are disclosed, including using a memory controller to partition a memory array into a first portion and a second portion, the first portion and second portion having non-overlapping logical block addressing (LBA) ranges. The memory controller assigns a first granularity of a first logical-to-physical (L2P) mapping table entry for the first portion of the memory array designated for a first usage, and a second granularity of a second L2P mapping table entry for the second portion of the memory array designated for a second usage, where the second granularity is not equal to the first granularity. The memory controller stores the first granularity and the second granularity in the memory array, and stores at least a portion of the first L2P mapping table entry and the second L2P mapping table entry in an L2P cache of the memory controller.
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公开(公告)号：US10901658B2
公开(公告)日：2021-01-26
申请号：US16235664
申请日：2018-12-28
Applicant: Micron Technology, Inc.
Inventor： Nadav Grosz , David Aaron Palmer
IPC: G06F3/06
Abstract: Devices and techniques for host adaptive memory device optimization are provided. A memory device can maintain a host model of interactions with a host. A set of commands from the host can be evaluated to create a profile of the set of commands. The profile can be compared to the host model to determine an inconsistency between the profile and the host model. An operation of the memory device can then be modified based on the inconsistency.
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公开(公告)号：US20200210107A1
公开(公告)日：2020-07-02
申请号：US16293227
申请日：2019-03-05
Applicant: Micron Technology, Inc.
Inventor： David Aaron Palmer
IPC: G06F3/06
Abstract: Devices and techniques for arbitrating operation of memory devices in a managed NAND memory system to conform the operation to a power budget. In an example, a method can include enabling a subset of memory die of a memory system having multiple memory die, starting an active timer for each active memory die, initializing execution of a buffered memory command at each active die based on a timestamp associated with the buffered memory command, and disabling a first memory die of the subset of memory die when the active timer for the first die expires to maintain compliance with a power budget of the memory system.
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公开(公告)号：US20200210097A1
公开(公告)日：2020-07-02
申请号：US16235168
申请日：2018-12-28
Applicant: Micron Technology, Inc
Inventor： Nadav Grosz , David Aaron Palmer
IPC: G06F3/06
Abstract: Devices and techniques for generating a response to a host with a memory device are provided. A first command from a host can be executed. A status for the first command can be determined. An inquiry from the host about a second command can be received after execution of the first command has begun. A response can be made to the inquiry that includes information about the second command and the status for the first command.
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