公开(公告)号：US20210103446A1

公开(公告)日：2021-04-08

申请号：US16592547

申请日：2019-10-03

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov ,  Samuel E. Bradshaw

IPC: G06F9/4401 ,  G06F9/445 ,  G06F12/06 ,  G06N3/08 ,  G06N3/04

Abstract: In a mobile device, processes of an application can be monitored and scored for initial data distribution. Specifically, a method can include monitoring processes of an application, and scoring objects or components used by the processes to determine placement of the objects or components in memory during initiation of the application. The method can also include, during initiation of the application, loading, into a first portion of the memory, at least partially, the objects or components scored at a first level. The method can also include, during initiation of the application, loading, into a second portion of the memory, at least partially, the objects or components scored at a second level. The objects or components scored at the second level can be less critical to the application than the objects or components scored at the first level.

公开(公告)号：US20210072986A1

公开(公告)日：2021-03-11

申请号：US16717890

申请日：2019-12-17

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov ,  Sean S. Eilert ,  Sivagnanam Parthasarathy ,  Shivasankar Gunasekaran ,  Ameen D. Akel

IPC: G06F9/30 ,  G11C7/06 ,  G11C7/10

Abstract: Methods, apparatuses, and systems for in- or near-memory processing are described. Strings of bits (e.g., vectors) may be fetched and processed in logic of a memory device without involving a separate processing unit. Operations (e.g., arithmetic operations) may be performed on numbers stored in a bit-serial way during a single sequence of clock cycles. Arithmetic may thus be performed in a single pass as numbers are bits of two or more strings of bits are fetched and without intermediate storage of the numbers. Vectors may be fetched (e.g., identified, transmitted, received) from one or more bit lines. Registers of the memory array may be used to write (e.g., store or temporarily store) results or ancillary bits (e.g., carry bits or carry flags) that facilitate arithmetic operations. Circuitry near, adjacent, or under the memory array may employ XOR or AND (or other) logic to fetch, organize, or operate on the data.

公开(公告)号：US20200382590A1

公开(公告)日：2020-12-03

申请号：US16424411

申请日：2019-05-28

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov ,  Ameen D. Akel ,  Samuel E. Bradshaw ,  Kenneth Marion Curewitz ,  Sean Stephen Eilert

IPC: H04L29/08 ,  G06F12/1027 ,  G06F12/1009 ,  G06F12/02

Abstract: Systems, methods and apparatuses to provide memory as a service are described. For example, a borrower device is configured to: communicate with a lender device; borrow an amount of memory from the lender device; expand memory capacity of the borrower device for applications running on the borrower device, using at least the local memory of the borrower device and the amount of memory borrowed from the lender device; and service accesses by the applications to memory via communication link between the borrower device and the lender device.

公开(公告)号：US20200379908A1

公开(公告)日：2020-12-03

申请号：US16424421

申请日：2019-05-28

Applicant: Micron Technology, Inc.

Inventor： Kenneth Marion Curewitz ,  Ameen D. Akel ,  Samuel E. Bradshaw ,  Sean Stephen Eilert ,  Dmitri Yudanov

IPC: G06F12/0837 ,  G06F12/1027 ,  G06F12/1009 ,  G06F11/14 ,  G06F9/38

Abstract: Systems, methods and apparatuses to intelligently migrate content involving borrowed memory are described. For example, after the prediction of a time period during which a network connection between computing devices having borrowed memory degrades, the computing devices can make a migration decision for content of a virtual memory address region, based at least in part on a predicted usage of content, a scheduled operation, a predicted operation, a battery level, etc. The migration decision can be made based on a memory usage history, a battery usage history, a location history, etc. using an artificial neural network; and the content migration can be performed by remapping virtual memory regions in the memory maps of the computing devices.

公开(公告)号：US12301659B2

公开(公告)日：2025-05-13

申请号：US17899265

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov ,  Ameen D. Akel ,  Samuel E. Bradshaw ,  Kenneth Marion Curewitz ,  Sean Stephen Eilert

IPC: G06F15/16 ,  G06F12/02 ,  G06F12/1009 ,  G06F12/1027 ,  H04L67/1097 ,  H04L67/51

Abstract: Systems, methods and apparatuses to provide memory as a service are described. For example, a borrower device is configured to: communicate with a lender device; borrow an amount of memory from the lender device; expand memory capacity of the borrower device for applications running on the borrower device, using at least the local memory of the borrower device and the amount of memory borrowed from the lender device; and service accesses by the applications to memory via communication link between the borrower device and the lender device.

公开(公告)号：US20240330667A1

公开(公告)日：2024-10-03

申请号：US18738644

申请日：2024-06-10

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov ,  Sean S. Eilert ,  Hernan A. Castro ,  William A. Melton

IPC: G06N3/063 ,  G06F3/06 ,  G06N3/04 ,  G11C7/06 ,  G11C8/08 ,  G11C11/54 ,  H03M1/46

CPC classification number: G06N3/063 ,  G06F3/0604 ,  G06F3/0661 ,  G06F3/0673 ,  G06N3/04 ,  G11C7/06 ,  G11C8/08 ,  G11C11/54 ,  H03M1/46

Abstract: Methods, apparatuses, and systems for in- or near-memory processing are described. Bits of a first number may be stored on a number of memory elements, wherein each memory element of the number of memory elements intersects a digit line and an access line of a number of access lines. A number of signals corresponding to bits of a second number may be driven on the number of access lines to generate a number of output signals. A value equal to a product of the first number and the second number may be generated based on the number of output signals.

公开(公告)号：US20240273349A1

公开(公告)日：2024-08-15

申请号：US18642669

申请日：2024-04-22

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov ,  Sean S. Eilert ,  Hernan A. Castro ,  Ameen D. Akel

IPC: G06N3/063 ,  G06N3/049 ,  G06N3/084 ,  G06N5/046 ,  G11C11/4063 ,  G11C11/54

CPC classification number: G06N3/063 ,  G06N3/049 ,  G11C11/4063 ,  G11C11/54 ,  G06N3/084 ,  G06N5/046

Abstract: Spiking events in a spiking neural network may be processed via a memory system. A memory system may store data corresponding to a group of destination neurons. The memory system may, at each time interval of a SNN, pass through data corresponding to a group of pre-synaptic spike events from respective source neurons. The data corresponding to the group of pre-synaptic spike events may be subsequently stored in the memory system.

公开(公告)号：US20240232601A1

公开(公告)日：2024-07-11

申请号：US18582467

申请日：2024-02-20

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov ,  Sean S. Eilert ,  Hernan A. Castro ,  Ameen D. Akel

IPC: G06N3/063 ,  G06F12/06 ,  G06N3/04

CPC classification number: G06N3/063 ,  G06F12/0646 ,  G06N3/04 ,  G06F2212/1008

Abstract: Methods, apparatuses, and systems for in- or near-memory processing are described. Spiking events in a spiking neural network may be processed via a memory system. A memory system may store a group of destination neurons, and at each time interval in a series of time intervals of a spiking neural network (SNN), pass through a group of pre-synaptic spike events from respective source neurons, wherein the group of pre-synaptic spike events are subsequently stored in memory.

公开(公告)号：US20240220205A1

公开(公告)日：2024-07-04

申请号：US18607653

申请日：2024-03-18

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov

IPC: G06F7/544 ,  G06F3/06 ,  G06F7/523 ,  G06N3/08

CPC classification number: G06F7/5443 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G06F7/523 ,  G06N3/08

Abstract: The present disclosure is directed to systems and methods for a memory device such as, for example, a Processing-In-Memory Device that is configured to perform multiplication operations in memory using a popcount operation. A multiplication operation may include a summation of multipliers being multiplied with corresponding multiplicands. The inputs may be arranged in particular configurations within a memory array. Sense amplifiers may be used to perform the popcount by counting active bits along bit lines. One or more registers may accumulate results for performing the multiplication operations.

公开(公告)号：US11941455B2

公开(公告)日：2024-03-26

申请号：US16713996

申请日：2019-12-13

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov

IPC: G06F9/50 ,  G06N20/00 ,  H04W88/08

CPC classification number: G06F9/5083 ,  G06N20/00 ,  H04W88/08

Abstract: Systems and methods for implementing shadow computations in base stations. The systems and methods can include a method including initiating, at a base station (such as a cellular base station), a shadow computation of a main computation executing for a mobile device. The main computation can include a computational task, and the shadow computation can be at least a part of or a derivative of the main computation. The method can also include executing, by the base station, the shadow computation.