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    Semiconductor memory device with read/write margin control using back-gate bias
    81.
    发明授权
    Semiconductor memory device with read/write margin control using back-gate bias 有权
    具有读/写裕度控制的半导体存储器件使用背栅极偏置

    公开(公告)号：US08125837B2

    公开(公告)日：2012-02-28

    申请号：US12543499

    申请日：2009-08-18

    申请人： Masanao Yamaoka ,  Kenichi Osada

    发明人： Masanao Yamaoka ,  Kenichi Osada

    IPC分类号： G11C11/00 ,  G11C7/10 ,  G11C5/14

    CPC分类号： G11C8/08 ,  G11C11/412

    摘要： The semiconductor device makes a comparison between a word-line timing signal for determining a word-line activation time and a reference signal, applies a back-gate bias for enlarging a read margin when the result of the comparison represents a low condition of the read margin, and applies a back-gate bias for enlarging a write margin when the comparison result represents a low condition of the write margin. The reference signal is selected depending on whether to compensate an operating margin fluctuating according to the word-line activation time (or word-line pulse width), or to compensate an operating margin fluctuating according to the process fluctuation (or variation in threshold voltage). By controlling the back-gate biases according to the word-line pulse width, an operating margin fluctuating according to the word-line pulse width, and an operating margin fluctuating owing to the variation in threshold voltage during its fabrication are improved.

    摘要翻译： 半导体器件在用于确定字线激活时间的字线定时信号与参考信号之间进行比较，当比较结果表示读取的低条件时，施加用于放大读取余量的反向栅极偏置 并且当比较结果表示写入余量的低条件时，施加用于扩大写入裕度的反向栅极偏置。 参考信号是根据是否补偿根据字线激活时间（或字线脉冲宽度）而波动的工作裕度，或者根据工艺波动（或阈值电压的变化）来补偿工作裕量波动， 。 通过根据字线脉冲宽度控制背栅极偏压，可以提高根据字线脉冲宽度而波动的工作裕度，以及由于其制造期间的阈值电压的变化而波动的工作裕度。

    SEMICONDUCTOR INTEGRATED CIRCUIT AND ITS CONTROL TECHNIQUE
    82.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT AND ITS CONTROL TECHNIQUE 审中-公开
    半导体集成电路及其控制技术

    公开(公告)号：US20110234297A1

    公开(公告)日：2011-09-29

    申请号：US13026241

    申请日：2011-02-12

    申请人： Tetsuya FUKUOKA ,  Yasuhiro Fujimura ,  Masanao Yamaoka

    发明人： Tetsuya FUKUOKA ,  Yasuhiro Fujimura ,  Masanao Yamaoka

    IPC分类号： H03K17/687

    CPC分类号： H03K19/0016 ,  H03K19/00361

    摘要： Provided is a control technique of a semiconductor integrated circuit capable by which power on/shut-off of a power shut-off area at an optimum speed in accordance with variations in fabricating devices as suppressing the malfunction of a circuit during operation in the power on/shut-off. A semiconductor integrated circuit includes: an always-on area; a power shut-off area; and a plurality of power-supply switches connected to the power shut-off area for supplying or shutting off the power to the power shut-off area.Further, the semiconductor integrated circuit includes a switch controller for carrying out the power on/shut-off by controlling on/off of the plurality of power-supply switches and changing the transition time of the power on/shut-off in accordance with a performance of each of the semiconductor integrated circuit after fabricating. Further, the semiconductor integrated circuit includes a memory for recording the performance of each of the semiconductor integrated circuit after fabricating.

    摘要翻译： 提供一种半导体集成电路的控制技术，其能够根据制造装置的变化以最佳速度接通/切断电源切断区域，以抑制电源操作期间电路的故障 /关闭。 一种半导体集成电路包括：永久接通区域; 电源关闭区; 以及连接到电源切断区域的多个电源开关，用于向电源切断区域供电或切断电源。 此外，半导体集成电路包括开关控制器，用于通过控制多个电源开关的接通/断开来实现电源接通/切断，并且根据一个电源开关改变电源接通/切断的转换时间 制造后的每个半导体集成电路的性能。 此外，半导体集成电路包括用于在制造之后记录每个半导体集成电路的性能的存储器。

    Semiconductor memory device
    83.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US07821814B2

    公开(公告)日：2010-10-26

    申请号：US12222753

    申请日：2008-08-15

    申请人： Masanao Yamaoka ,  Kenichi Osada ,  Kazumasa Yanagisawa

    发明人： Masanao Yamaoka ,  Kenichi Osada ,  Kazumasa Yanagisawa

    IPC分类号： G11C11/00 ,  G11C5/14

    CPC分类号： G11C11/417 ,  G11C5/14 ,  G11C5/148

    摘要： When threshold voltages of constituent transistors are reduced in order to operate an SRAM circuit at a low voltage, there is a problem in that a leakage current of the transistors is increased and, as a result, electric power consumption when the SRAM circuit is not operated while storing data is increased. Therefore, there is provided a technique for reducing the leakage current of MOS transistors in SRAM memory cells MC by controlling a potential of a source line ssl of the driver MOS transistors in the memory cells.

    摘要翻译： 当降低构成晶体管的阈值电压以便在低电压下操作SRAM电路时，存在晶体管的漏电流增加的问题，结果是当SRAM电路不工作时的功耗 同时存储数据增加。 因此，提供了通过控制存储单元中的驱动器MOS晶体管的源极线ssl的电位来减小SRAM存储单元MC中的MOS晶体管的漏电流的技术。

    Semiconductor device and semiconductor integrated circuit using the same
    84.
    发明授权
    Semiconductor device and semiconductor integrated circuit using the same 失效

    公开(公告)号：US07732864B2

    公开(公告)日：2010-06-08

    申请号：US11492054

    申请日：2006-07-25

    申请人： Takayuki Kawahara ,  Masanao Yamaoka

    发明人： Takayuki Kawahara ,  Masanao Yamaoka

    IPC分类号： H01L23/62

    CPC分类号： H01L27/1203 ,  H01L29/78645 ,  H01L29/78648

    摘要： The present invention provides a high speed and low power consumption LSI operable in a wide temperature range in which a MOS transistor having back gates is used specifically according to operating characteristics of a circuit.In the LSI, an FD-SOI structure having an embedded oxide film layer is used and a lower semiconductor region of the embedded oxide film layer is used as a back gate. A voltage for back gates in the logic circuits having a small load in the logic circuit block is controlled in response to activation of the block from outside of the block. Transistors, in which the gate and the back gate are connected to each other, are used for the circuit generating the back gate driving signal, and logic circuits having a heavy load such as circuit block output section, and the back gates are directly controlled according to the gate input signal.

    Semiconductor memory device
    85.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US07639525B2

    公开(公告)日：2009-12-29

    申请号：US11541542

    申请日：2006-10-03

    申请人： Masanao Yamaoka ,  Takayuki Kawahara

    发明人： Masanao Yamaoka ,  Takayuki Kawahara

    IPC分类号： G11C11/00 ,  G11C5/06 ,  G11C11/34 ,  G11C5/14

    CPC分类号： G11C11/412

    摘要： A semiconductor memory device for reducing the power consumption of an entire low power consumption SRAM LSI circuit employing scaled-down transistors and of increasing the stability of read and write operations on the memory cells by reducing the subthreshold leakage current and the leakage current flowing from the drain electrode to the substrate electrode is provided. The semiconductor memory device also prevents an increase in the number of transistors in a memory cell and thereby preventing an increase in the cell area, and ensures stable operation of an SRAM memory cell made up of SOI or FD-SOI transistors having a BOX layer by controlling the potentials of the wells under the BOX layers of the drive transistors.

    摘要翻译： 一种半导体存储器件，用于降低使用按比例缩小晶体管的整个低功耗SRAM LSI电路的功耗，并且通过减少亚阈值漏电流和从该存储器单元流出的漏电流来增加对存储单元的读和写操作的稳定性 漏电极到基板电极。 半导体存储器件还防止了存储单元中的晶体管数量的增加，从而防止了单元面积的增加，并且确保由具有BOX层的SOI或FD-SOI晶体管构成的SRAM存储单元的稳定工作由 控制驱动晶体管的BOX层下的阱的电位。

    Semiconductor memory device with memory cells operated by boosted voltage
    86.
    发明授权
    Semiconductor memory device with memory cells operated by boosted voltage 有权
    具有由升压电压工作的存储单元的半导体存储器件

    公开(公告)号：US07589993B2

    公开(公告)日：2009-09-15

    申请号：US12133343

    申请日：2008-06-04

    申请人： Masanao Yamaoka ,  Kenichi Osada ,  Koichiro Ishibashi

    发明人： Masanao Yamaoka ,  Kenichi Osada ,  Koichiro Ishibashi

    IPC分类号： G11C11/00

    CPC分类号： G11C11/417 ,  G11C11/412 ,  Y10S257/903

    摘要： A memory using an SRAM memory cell intended for low-voltage operation is designed to decrease the threshold value of MOS transistors constituting the memory cell without substantial decrease in the static noise margin, which is the operational margin of the memory cell. To this end, a voltage Vdd′ higher than a power supply voltage Vdd of a power supply line for peripheral circuits is supplied from a power supply line for memory cells as a power supply voltage for memory cells. Since the conductance of driver MOS transistors is in-creased, the threshold voltage of the MOS transistors within the memory cells can be reduced without reducing the static noise margin. Further the ratio of width between the driver MOS transistor and a transfer MOS transistor can be set to 1, thereby allowing a reduction in the memory cell area.

    摘要翻译： 使用用于低电压操作的SRAM存储单元的存储器被设计为降低构成存储器单元的MOS晶体管的阈值，而不会显着降低静态噪声容限，这是存储单元的操作余量。 为此，作为存储单元的电源电压，从用于存储单元的电源线提供高于外围电路用电源线的电源电压Vdd的电压Vdd'。 由于驱动器MOS晶体管的电导被增加，所以可以在不降低静态噪声容限的情况下减小存储单元内的MOS晶体管的阈值电压。 此外，可以将驱动器MOS晶体管和转移MOS晶体管之间的宽度比设置为1，从而允许存储单元区域的减小。

    Semiconductor memory device
    89.
    发明申请
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US20070076467A1

    公开(公告)日：2007-04-05

    申请号：US11541542

    申请日：2006-10-03

    申请人： Masanao Yamaoka ,  Takayuki Kawahara

    发明人： Masanao Yamaoka ,  Takayuki Kawahara

    IPC分类号： G11C11/00

    CPC分类号： G11C11/412

    摘要： An object of the present invention is to provide a technique of reducing the power consumption of an entire low power consumption SRAM LSI circuit employing scaled-down transistors and of increasing the stability of read and write operations on the memory cells by reducing the subthreshold leakage current and the leakage current flowing from the drain electrode to the substrate electrode. Another object of the present invention is to provide a technique of preventing an increase in the number of transistors in a memory cell and thereby preventing an increase in the cell area. Still another object of the present invention is to provide a technique of ensuring stable operation of an SRAM memory cell made up of SOI or FD-SOI transistors having a BOX layer by controlling the potentials of the wells under the BOX layers of the drive transistors.

    摘要翻译： 本发明的目的是提供一种降低使用按比例缩小的晶体管的整个低功耗SRAM LSI电路的功耗的技术，并且通过减少亚阈值泄漏电流来增加对存储单元的读和写操作的稳定性 以及从漏极流到基板电极的漏电流。 本发明的另一个目的是提供一种防止存储单元中的晶体管数量增加从而防止单元区域增加的技术。 本发明的另一个目的是提供一种通过控制驱动晶体管的BOX层下的阱的电位来确保由具有BOX层的SOI或FD-SOI晶体管构成的SRAM存储单元的稳定工作的技术。