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公开(公告)号：US20110234297A1
公开(公告)日：2011-09-29
申请号：US13026241
申请日：2011-02-12
IPC分类号： H03K17/687
CPC分类号： H03K19/0016 , H03K19/00361
摘要： Provided is a control technique of a semiconductor integrated circuit capable by which power on/shut-off of a power shut-off area at an optimum speed in accordance with variations in fabricating devices as suppressing the malfunction of a circuit during operation in the power on/shut-off. A semiconductor integrated circuit includes: an always-on area; a power shut-off area; and a plurality of power-supply switches connected to the power shut-off area for supplying or shutting off the power to the power shut-off area.Further, the semiconductor integrated circuit includes a switch controller for carrying out the power on/shut-off by controlling on/off of the plurality of power-supply switches and changing the transition time of the power on/shut-off in accordance with a performance of each of the semiconductor integrated circuit after fabricating. Further, the semiconductor integrated circuit includes a memory for recording the performance of each of the semiconductor integrated circuit after fabricating.
摘要翻译： 提供一种半导体集成电路的控制技术，其能够根据制造装置的变化以最佳速度接通/切断电源切断区域，以抑制电源操作期间电路的故障 /关闭。 一种半导体集成电路包括：永久接通区域; 电源关闭区; 以及连接到电源切断区域的多个电源开关，用于向电源切断区域供电或切断电源。 此外，半导体集成电路包括开关控制器，用于通过控制多个电源开关的接通/断开来实现电源接通/切断，并且根据一个电源开关改变电源接通/切断的转换时间 制造后的每个半导体集成电路的性能。 此外，半导体集成电路包括用于在制造之后记录每个半导体集成电路的性能的存储器。
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2.发明授权公开(公告)号：US08350409B2
公开(公告)日：2013-01-08
申请号：US12759520
申请日：2010-04-13
IPC分类号： H02J1/10
CPC分类号： G06F1/32 , G06F1/3287 , Y02D10/171 , Y10T307/50
摘要： Objects of the invention are to minimize power consumption while maintaining the required information processing capabilities of an LSI chip by supplying multiple voltages to the LSI chip such that its circuit blocks receive necessary voltages and to prevent an increase in the chip area of the LSI chip and performance degradation of signal wires, which may result from the supply of the multiple voltages, by reducing the number of power supply wires.In an LSI chip to which two voltages are supplied, high voltage wires are more densely spaced than low voltage wires. By selectively applying voltages based on circuit block performance, it is possible to reduce power consumption while maintaining the amount of information processed by the LSI chip.
摘要翻译： 本发明的目的是通过向LSI芯片提供多个电压使得其电路块接收必要的电压并防止LSI芯片的芯片面积的增加来保持LSI芯片所需的信息处理能力，从而最小化功耗，并且 通过减少电源线的数量，可能由多个电压的供给引起的信号线的性能下降。 在提供两个电压的LSI芯片中，高压电线与低压电线相比密度更高。 通过基于电路块性能选择性地施加电压，可以在保持由LSI芯片处理的信息量的同时降低功耗。
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公开(公告)号：US20100264735A1
公开(公告)日：2010-10-21
申请号：US12759520
申请日：2010-04-13
IPC分类号： H02J1/10
CPC分类号： G06F1/32 , G06F1/3287 , Y02D10/171 , Y10T307/50
摘要： Objects of the invention are to minimize power consumption while maintaining the required information processing capabilities of an LSI chip by supplying multiple voltages to the LSI chip such that its circuit blocks receive necessary voltages and to prevent an increase in the chip area of the LSI chip and performance degradation of signal wires, which may result from the supply of the multiple voltages, by reducing the number of power supply wires.In an LSI chip to which two voltages are supplied, high voltage wires are more densely spaced than low voltage wires. By selectively applying voltages based on circuit block performance, it is possible to reduce power consumption while maintaining the amount of information processed by the LSI chip.
摘要翻译： 本发明的目的是通过向LSI芯片提供多个电压使得其电路块接收必要的电压并防止LSI芯片的芯片面积的增加来保持LSI芯片所需的信息处理能力，从而最小化功耗，并且 通过减少电源线的数量，可能由多个电压的供给引起的信号线的性能下降。 在提供两个电压的LSI芯片中，高压电线与低压电线相比密度更高。 通过基于电路块性能选择性地施加电压，可以在保持由LSI芯片处理的信息量的同时降低功耗。
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公开(公告)号：US07612599B2
公开(公告)日：2009-11-03
申请号：US12167233
申请日：2008-07-02
IPC分类号： H03K3/00
CPC分类号： G06F1/10
摘要： Clock skew can be reduced by suppressing fluctuation in wiring leads between the final stage clock buffers and the clock distribution circuit for supplying the clock. In view of attaining such reduction of clock skew, an upstream of the clock distribution circuit is formed in an H tree structure and the final stage is formed in a local fishbone structure. A plurality of main clock lines connected to the final stage buffer include a first main clock line and a second main clock line. The number of cell arrangement allowable rows where a plurality of first flip-flops for receiving the clock from the first main clock line are located is different from the number of cell arrangement allowable rows where a plurality first flip-flops for receiving the clock from the second main clock line are located.
摘要翻译： 可以通过抑制最终级时钟缓冲器和用于提供时钟的时钟分配电路之间的布线引线的波动来减小时钟偏移。 考虑到实现时钟偏移的这种减少，时钟分配电路的上游形成为H树结构，并且最终级形成在局部鱼骨结构中。 连接到最后级缓冲器的多个主时钟线包括第一主时钟线和第二主时钟线。 用于从第一主时钟线接收时钟的多个第一触发器所在的单元布置允许行的数量不同于用于从第一主时钟线接收时钟的多个第一触发器的单元布置允许行数 第二主时钟线位于。
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公开(公告)号：US5583817A
公开(公告)日：1996-12-10
申请号：US382592
申请日：1995-02-02
CPC分类号： G11C7/1051 , G11C29/36
摘要： Read signals to be outputted in the unit of bits from a packaged RAM are received to produce complementary output signals, and these output signals and the non-inverted and inverted signals of expected values are individually inputted to two logic circuits, so that the outputs of the logic circuits are compared by a coincidence/incoincidence circuit to produce a decision output.
摘要翻译： 接收从封装的RAM以位为单位输出的读出信号，以产生互补的输出信号，这些输出信号和预期值的非反相和反相信号被分别输入到两个逻辑电路，使得输出 逻辑电路通过符合/不一致电路进行比较，以产生决策输出。
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公开(公告)号：US07894133B2
公开(公告)日：2011-02-22
申请号：US11868048
申请日：2007-10-05
IPC分类号： G02B5/30
CPC分类号： G02B5/1809 , G02B5/1866 , G02B5/3083
摘要： A disclosed optical element includes: a transparent substrate; a subwavelength structure layer disposed on the transparent substrate, the subwavelength structure layer having a refractive index different from a refractive index of the transparent substrate; a minute concave and convex structure of one-dimensional grating formed on the subwavelength structure layer with a subwavelength period smaller than a wavelength to be used, where a concave portion reaches a boundary surface between the transparent substrate and the subwavelength structure layer; and an open hole portion formed on a subwavelength structure layer side of the transparent substrate so as to communicate with the concave portion of the minute structure and to be arranged with the same period as in the minute structure of one-dimensional grating. At least at the open hole portion, a refractive index relative to an incident light is changed in a direction orthogonal to the boundary surface.
摘要翻译： 所公开的光学元件包括：透明基板; 设置在所述透明基板上的亚波长结构层，所述亚波长结构层的折射率不同于所述透明基板的折射率; 形成在亚波长结构层上的亚波长时间段小于要使用的波长的一维光栅的微小凹凸结构，其中凹部到达透明基板和亚波长结构层之间的边界面; 以及开口部，形成在透明基板的亚波长结构层侧，以与微细结构的凹部连通并且与一维光栅的微小结构相同的周期配置。 至少在开孔部分，相对于入射光的折射率在与边界表面正交的方向上变化。
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公开(公告)号：US20080106789A1
公开(公告)日：2008-05-08
申请号：US11868048
申请日：2007-10-05
IPC分类号： G02B5/18
CPC分类号： G02B5/1809 , G02B5/1866 , G02B5/3083
摘要： A disclosed optical element includes: a transparent substrate; a subwavelength structure layer disposed on the transparent substrate, the subwavelength structure layer having a refractive index different from a refractive index of the transparent substrate; a minute concave and convex structure of one-dimensional grating formed on the subwavelength structure layer with a subwavelength period smaller than a wavelength to be used, where a concave portion reaches a boundary surface between the transparent substrate and the subwavelength structure layer; and an open hole portion formed on a subwavelength structure layer side of the transparent substrate so as to communicate with the concave portion of the minute structure and to be arranged with the same period as in the minute structure of one-dimensional grating. At least at the open hole portion, a refractive index relative to an incident light is changed in a direction orthogonal to the boundary surface.
摘要翻译： 所公开的光学元件包括：透明基板; 设置在所述透明基板上的亚波长结构层，所述亚波长结构层的折射率不同于所述透明基板的折射率; 形成在亚波长结构层上的亚波长时间段小于要使用的波长的一维光栅的微小凹凸结构，其中凹部到达透明基板和亚波长结构层之间的边界面; 以及开口部，形成在透明基板的亚波长结构层侧，以与微细结构的凹部连通并且与一维光栅的微小结构相同的周期配置。 至少在开孔部分，相对于入射光的折射率在与边界表面正交的方向上变化。
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8.发明授权Method and arrangement of locating cordless units in wide area cordless telephone system 失效在广域无绳电话系统中定位无绳单元的方法和布置
公开(公告)号：US5442684A
公开(公告)日：1995-08-15
申请号：US181878
申请日：1994-01-13
申请人： Tadao Hashimoto , Ryoji Hara , Yasuhiro Fujimura
发明人： Tadao Hashimoto , Ryoji Hara , Yasuhiro Fujimura
摘要： A method and arrangement of locating cordless units in a wide area cordless telephone system is disclosed. A service area is previously divided into a plurality of small service zones and, a plurality of cordless units are provided for establishing communications with a system controller via a plurality of access stations. The system controller locates the cordless units and stores therein location data thereof. Each of the cordless units also stores the location data thereof applied from the system controller. A cordless unit issues a request signal which includes cordless unit location data. The request signal is received at an access station which in turn checks to determine if the request signal applied thereto is issued from a cordless unit whose location data indicates a service zone belonging to a predetermined service zone group. In the event that the cordless unit location data applied to the access station is found to fall within the predetermined service zone group, the access station relays the request signal applied thereto, together with a signal level of the request signal, to the system controller.
摘要翻译： 公开了一种在广域无绳电话系统中定位无绳单元的方法和装置。 服务区域先前被划分为多个小服务区域，并且提供多个无绳单元，用于经由多个接入站与系统控制器建立通信。 系统控制器定位无绳单元并存储其中的位置数据。 每个无绳单元还存储从系统控制器应用的位置数据。 无绳单元发出包括无绳单元位置数据的请求信号。 该请求信号在接入站接收，接入站进一步检查确定是否从其位置数据指示属于预定服务区域组的服务区的无绳单元发出施加的请求信号。 在应用于接入站的无绳单元位置数据被发现落在预定服务区域组内的情况下，接入站将应用于其的请求信号与请求信号的信号电平中继到系统控制器。
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公开(公告)号：US08050333B2
公开(公告)日：2011-11-01
申请号：US11777181
申请日：2007-07-12
申请人： Takashi Muto , Yasuhiro Fujimura , Keiichi Higeta , Junji Baba , Takayuki Muranaka , Isao Kimura
发明人： Takashi Muto , Yasuhiro Fujimura , Keiichi Higeta , Junji Baba , Takayuki Muranaka , Isao Kimura
IPC分类号： H04L25/00
CPC分类号： H04L25/0274 , H04L25/0288
摘要： In a data transfer device which cancells an offset of a differential amplifier for amplifying a received signal and an offset caused by characteristics of a differential transmission line and selects optimum conditions such as pre-emphasis amount of an output pre-emphasis circuit, a first chip (transmission side LSI=transfer engine 210) and a second chip (reception side LSI=multiplexing engine 330) are connected to each other through differential transmission line 430 and a SerDes (serializer) 401 and a SerDes (deserializer) 402 are used to make signal transmission, so that optimum setting conditions of an offset amount of an offset cancellation circuit included in an input buffer amplifier and a pre-emphasis amount of pre-emphasis circuit included in an output buffer are decided in training using a training PRBS generator 560 and a training PRBS comparator 570.
摘要翻译： 在消除用于放大接收信号的差分放大器的偏移的数据传送装置和由差分传输线的特性引起的偏移，并且选择诸如输出预加重电路的预加重量之类的最佳条件，第一芯片 （发送侧LSI =传送引擎210）和第二芯片（接收侧LSI =多路复用引擎330）通过差分传输线路430彼此连接，并且使用SerDes（串行器）401和SerDes（解串器）402来进行 信号传输，使得包括在输入缓冲放大器中的偏移消除电路的偏移量的最佳设置条件和包括在输出缓冲器中的预加重电路的预加重量在训练中使用训练PRBS发生器560和 训练PRBS比较器570。
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公开(公告)号：US20090079488A1
公开(公告)日：2009-03-26
申请号：US12167233
申请日：2008-07-02
IPC分类号： G06F1/04
CPC分类号： G06F1/10
摘要： Clock skew can be reduced by suppressing fluctuation in wiring leads between the final stage clock buffers and the clock distribution circuit for supplying the clock. In view of attaining such reduction of clock skew, an upstream of the clock distribution circuit is formed in an H tree structure and the final stage is formed in a local fishbone structure. A plurality of main clock lines connected to the final stage buffer include a first main clock line and a second main clock line. The number of cell arrangement allowable rows where a plurality of first flip-flops for receiving the clock from the first main clock line are located is different from the number of cell arrangement allowable rows where a plurality first flip-flops for receiving the clock from the second main clock line are located.
摘要翻译： 可以通过抑制最终级时钟缓冲器和用于提供时钟的时钟分配电路之间的布线引线的波动来减小时钟偏移。 考虑到实现时钟偏移的这种减少，时钟分配电路的上游形成为H树结构，并且最终级形成在局部鱼骨结构中。 连接到最后级缓冲器的多个主时钟线包括第一主时钟线和第二主时钟线。 用于从第一主时钟线接收时钟的多个第一触发器所在的单元布置允许行的数量不同于用于从第一主时钟线接收时钟的多个第一触发器的单元布置允许行数 第二主时钟线位于。
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