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公开(公告)号：US20110234297A1
公开(公告)日：2011-09-29
申请号：US13026241
申请日：2011-02-12
IPC分类号： H03K17/687
CPC分类号： H03K19/0016 , H03K19/00361
摘要： Provided is a control technique of a semiconductor integrated circuit capable by which power on/shut-off of a power shut-off area at an optimum speed in accordance with variations in fabricating devices as suppressing the malfunction of a circuit during operation in the power on/shut-off. A semiconductor integrated circuit includes: an always-on area; a power shut-off area; and a plurality of power-supply switches connected to the power shut-off area for supplying or shutting off the power to the power shut-off area.Further, the semiconductor integrated circuit includes a switch controller for carrying out the power on/shut-off by controlling on/off of the plurality of power-supply switches and changing the transition time of the power on/shut-off in accordance with a performance of each of the semiconductor integrated circuit after fabricating. Further, the semiconductor integrated circuit includes a memory for recording the performance of each of the semiconductor integrated circuit after fabricating.
摘要翻译： 提供一种半导体集成电路的控制技术，其能够根据制造装置的变化以最佳速度接通/切断电源切断区域，以抑制电源操作期间电路的故障 /关闭。 一种半导体集成电路包括：永久接通区域; 电源关闭区; 以及连接到电源切断区域的多个电源开关，用于向电源切断区域供电或切断电源。 此外，半导体集成电路包括开关控制器，用于通过控制多个电源开关的接通/断开来实现电源接通/切断，并且根据一个电源开关改变电源接通/切断的转换时间 制造后的每个半导体集成电路的性能。 此外，半导体集成电路包括用于在制造之后记录每个半导体集成电路的性能的存储器。
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2.发明授权公开(公告)号：US08350409B2
公开(公告)日：2013-01-08
申请号：US12759520
申请日：2010-04-13
IPC分类号： H02J1/10
CPC分类号： G06F1/32 , G06F1/3287 , Y02D10/171 , Y10T307/50
摘要： Objects of the invention are to minimize power consumption while maintaining the required information processing capabilities of an LSI chip by supplying multiple voltages to the LSI chip such that its circuit blocks receive necessary voltages and to prevent an increase in the chip area of the LSI chip and performance degradation of signal wires, which may result from the supply of the multiple voltages, by reducing the number of power supply wires.In an LSI chip to which two voltages are supplied, high voltage wires are more densely spaced than low voltage wires. By selectively applying voltages based on circuit block performance, it is possible to reduce power consumption while maintaining the amount of information processed by the LSI chip.
摘要翻译： 本发明的目的是通过向LSI芯片提供多个电压使得其电路块接收必要的电压并防止LSI芯片的芯片面积的增加来保持LSI芯片所需的信息处理能力，从而最小化功耗，并且 通过减少电源线的数量，可能由多个电压的供给引起的信号线的性能下降。 在提供两个电压的LSI芯片中，高压电线与低压电线相比密度更高。 通过基于电路块性能选择性地施加电压，可以在保持由LSI芯片处理的信息量的同时降低功耗。
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公开(公告)号：US20110115474A1
公开(公告)日：2011-05-19
申请号：US12917523
申请日：2010-11-02
IPC分类号： G01R5/14
CPC分类号： G06F1/3203 , G06F1/206 , H01L21/67276 , Y02D10/16
摘要： To provide an LSI having a low power mode that can prevent an apparatus on which the LSI is mounted from resulting in performance degradation, etc. even when its electric power is not reduced in the low power mode. Devised is a circuit that instructs an operation mode and detects whether the LSI operates as specified by the mode, and that measures a current at the time of the low power mode in a pseudo manner and, if despite having shifted to the low power mode, the current is not reduced actually, issues an alarm signal.
摘要翻译： 为了提供具有低功率模式的LSI，即使在低功率模式下其电力没有降低的情况下，也可以防止LSI的装置在其中导致性能劣化等。 设计的是指示操作模式并且检测LSI是否以模式指定的方式操作的电路，并且以伪方式测量低功率模式时的电流，并且如果尽管已经转移到低功率模式， 电流实际上没有减少，发出报警信号。
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公开(公告)号：US08633684B2
公开(公告)日：2014-01-21
申请号：US12917523
申请日：2010-11-02
IPC分类号： G01R5/14
CPC分类号： G06F1/3203 , G06F1/206 , H01L21/67276 , Y02D10/16
摘要： To provide an LSI having a low power mode that can prevent an apparatus on which the LSI is mounted from resulting in performance degradation, etc. even when its electric power is not reduced in the low power mode. Devised is a circuit that instructs an operation mode and detects whether the LSI operates as specified by the mode, and that measures a current at the time of the low power mode in a pseudo manner and, if despite having shifted to the low power mode, the current is not reduced actually, issues an alarm signal.
摘要翻译： 为了提供具有低功率模式的LSI，即使在低功率模式下其电力没有降低的情况下，也可以防止LSI的装置在其中导致性能劣化等。 设计的是指示操作模式并且检测LSI是否以模式指定的方式操作的电路，并且以伪方式测量低功率模式时的电流，并且如果尽管已经转移到低功率模式， 电流实际上没有减少，发出报警信号。
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公开(公告)号：US08451050B2
公开(公告)日：2013-05-28
申请号：US12987112
申请日：2011-01-08
IPC分类号： G05F1/10
CPC分类号： G06F1/3203 , H03K19/0016
摘要： Information technology equipment includes a circuit block, a local power source line for supplying a power source to the circuit block, a power source line, and a first transistor which is provided with a source-drain path thereof between the power source line and the local power source line, in which the first transistor is controlled to an OFF state in a first state, and is controlled to an ON state in a second state, and when the first state is shifted to the second state, the first transistor is controlled such that a rate of changing a current flowing in the source-drain path of the first transistor does not exceed a predetermined value.
摘要翻译： 信息技术设备包括电路块，用于向电路块提供电源的局部电源线，电源线和在电源线和本地电源线之间设置有源极 - 漏极路径的第一晶体管 电源线，其中第一晶体管在第一状态下被控制为OFF状态，并且在第二状态下被控制为ON状态，并且当第一状态转移到第二状态时，第一晶体管被控制为 改变在第一晶体管的源极 - 漏极路径中流动的电流的速率不超过预定值。
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公开(公告)号：US20150212570A1
公开(公告)日：2015-07-30
申请号：US14424145
申请日：2012-09-03
申请人： Masaki Hamamoto , Masanao Yamaoka
发明人： Masaki Hamamoto , Masanao Yamaoka
IPC分类号： G06F1/32
CPC分类号： G06F1/3243 , Y02D10/152
摘要： In the related art, even in computation of an application which has a resistance to a computation error in a computer system, since the computation error is accurately corrected, there is a problem that a power supply voltage or an operating frequency for realizing lower power or a faster speed cannot be variable in a large manner.In the invention, it is possible to solve the above-described problem by a computer system which includes a first processor and a second processor. In the first processor, at least one of an operating frequency or an operating voltage is variable. A detecting module which is operated by the second processor detects an error of the first processor. A determining module which is operated by the second processor determines at least one of the operating frequency or the operating voltage of the first processor.
摘要翻译： 在现有技术中，即使在对计算机系统中具有计算误差的抵抗力的应用的计算中，由于计算误差被精确地校正，所以存在用于实现较低功率的电源电压或工作频率的问题， 更快的速度不能大的变化。 在本发明中，可以通过包括第一处理器和第二处理器的计算机系统来解决上述问题。 在第一处理器中，工作频率或工作电压中的至少一个是可变的。 由第二处理器操作的检测模块检测第一处理器的错误。 由第二处理器操作的确定模块确定第一处理器的工作频率或工作电压中的至少一个。
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公开(公告)号：US08508968B2
公开(公告)日：2013-08-13
申请号：US13461848
申请日：2012-05-02
CPC分类号： H01L25/0657 , G11C5/02 , H01L25/18 , H01L2224/16 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/13091 , H01L2924/15311 , H01L2924/00 , H01L2224/05599
摘要： The need for mediation operation is eliminated by adoption of a connection topology in which a circuit for executing one transmission (TR—00T), and a circuit for executing a plurality of receptions (TR—10R, TR—20R, TR—30R) are connected to one penetration-electrode group (for example, TSVGL—0). In order to implement the connection topology even in the case of piling up a plurality of LSIs one after another, in particular, a programmable memory element for designating respective penetration-electrode ports for use in transmit, or for us in receive, and address allocation of the respective penetration-electrode ports is mounted in stacked LSIs.
摘要翻译： 通过采用其中执行一次发送的电路（TR-00T）和用于执行多个接收（TR-10R，TR-20R，TR-30R）的电路的连接拓扑结构来消除对中介操作的需要 连接到一个穿透电极组（例如，TSVGL-0）。 为了实现连接拓扑，即使在堆叠多个LSI的情况下，尤其是用于指定用于发送的各个穿透电极端口或用于接收的可编程存储器元件，以及地址分配 各个贯通电极端口安装在堆叠的LSI中。
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公开(公告)号：US07995377B2
公开(公告)日：2011-08-09
申请号：US12624272
申请日：2009-11-23
申请人： Masanao Yamaoka , Takayuki Kawahara
发明人： Masanao Yamaoka , Takayuki Kawahara
CPC分类号： G11C11/412
摘要： An object of the present invention is to provide a technique of reducing the power consumption of an entire low power consumption SRAM LSI circuit employing scaled-down transistors and of increasing the stability of read and write operations on the memory cells by reducing the subthreshold leakage current and the leakage current flowing from the drain electrode to the substrate electrode.Another object of the present invention is to provide a technique of preventing an increase in the number of transistors in a memory cell and thereby preventing an increase in the cell area.Still another object of the present invention is to provide a technique of ensuring stable operation of an SRAM memory cell made up of SOI or FD-SOI transistors having a BOX layer by controlling the potentials of the wells under the BOX layers of the drive transistors.
摘要翻译： 本发明的目的是提供一种降低使用按比例缩小的晶体管的整个低功耗SRAM LSI电路的功耗的技术，并且通过减少亚阈值泄漏电流来增加对存储单元的读和写操作的稳定性 以及从漏极流到基板电极的漏电流。 本发明的另一个目的是提供一种防止存储单元中的晶体管数量增加从而防止单元区域增加的技术。 本发明的另一个目的是提供一种通过控制驱动晶体管的BOX层下的阱的电位来确保由具有BOX层的SOI或FD-SOI晶体管构成的SRAM存储单元的稳定工作的技术。
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公开(公告)号：US07961545B2
公开(公告)日：2011-06-14
申请号：US12629981
申请日：2009-12-03
IPC分类号： G11C5/14
CPC分类号： G11C11/419 , G11C5/146 , G11C5/147 , G11C11/4125 , G11C11/417 , G11C2207/2227
摘要： A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.
摘要翻译： 系统LSI中的逻辑电路设置有电源开关，以便在待机时切断开关，从而减少漏电流。 同时，系统LSI的SRAM电路控制衬底偏置以减少漏电流。
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公开(公告)号：US07911221B2
公开(公告)日：2011-03-22
申请号：US12335331
申请日：2008-12-15
申请人： Masanao Yamaoka , Kenichi Osada
发明人： Masanao Yamaoka , Kenichi Osada
IPC分类号： H03K19/00
CPC分类号： H03K19/00346
摘要： A speed performance measurement circuit that may perform speed performance measurement is provided between a first logic circuit and a second logic circuit. The speed performance measurement circuit includes a first flip flop that stores first data, a first delay circuit that delays the first data and generates second data, and a second flip flop that stores the second data. Furthermore, the speed performance measurement circuit includes a first comparator circuit that compares output of the first flip flop to output of the second flip flop, and a third flip flop that stores output data from the first comparator circuit in accordance with timing of the first clock signal. Data in a normal path is compared to data in a path delayed by a certain time to measure speed, and power voltage of a circuit is determined based on such comparison. Thus, change in speed with respect to power voltage in a critical path can be measured.
摘要翻译： 可以在第一逻辑电路和第二逻辑电路之间提供可执行速度性能测量的速度性能测量电路。 速度性能测量电路包括存储第一数据的第一触发器，延迟第一数据并产生第二数据的第一延迟电路和存储第二数据的第二触发器。 此外，速度性能测量电路包括第一比较器电路，其将第一触发器的输出与第二触发器的输出进行比较;以及第三触发器，其根据第一时钟的定时存储来自第一比较器电路的输出数据 信号。 将正常路径中的数据与延迟一定时间的路径中的数据进行比较以测量速度，并且基于这样的比较确定电路的功率电压。 因此，可以测量关键路径中的功率电压的速度变化。
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