公开(公告)号：US06891755B2

公开(公告)日：2005-05-10

申请号：US10340207

申请日：2003-01-10

申请人： Andrea Silvagni ,  Rino Micheloni ,  Giovanni Campardo

发明人： Andrea Silvagni ,  Rino Micheloni ,  Giovanni Campardo

IPC分类号： G11C16/08 ,  G11C16/04

CPC分类号： G11C16/08 ,  G11C2216/22

摘要： A memory device includes an array of memory cells organized into a plurality of sectors, and local wordlines and local bitlines are connected to the memory cells in each respective sector. Main read wordlines and main program wordlines are connected to the local wordlines in each sector. A main read row decoder is connected to the main read wordlines, and a main program row decoder connected to the main program wordlines. Main read bitlines and main program bitlines are connected to the local bitlines in each sector. A main read column decoder is connected to the main read bitlines, and a main program column decoder is connected to the main program wordlines. A read address bus is connected to the main read row decoder and to the main read column decoder for providing an address thereto. A program address bus is connected to the main read column decoder and to the main program row decoder for providing an address thereto.

摘要翻译： 存储器件包括组织成多个扇区的存储器单元的阵列，并且本地字线和本地位线连接到每个相应扇区中的存储器单元。 主读取字线和主程序字线连接到每个扇区中的本地字线。 主读取行解码器连接到主读取字线，连接到主程序字线的主程序行解码器。 主读位线和主程序位线连接到每个扇区中的本地位线。 主读取列解码器连接到主读取位线，主程序列解码器连接到主程序字线。 读地址总线连接到主读行解码器和主读列解码器，以提供地址。 程序地址总线连接到主读取列解码器和主程序行解码器，以向其提供地址。

公开(公告)号：US06829168B2

公开(公告)日：2004-12-07

申请号：US10334126

申请日：2002-12-30

申请人： Rino Micheloni ,  Giovanni Campardo

发明人： Rino Micheloni ,  Giovanni Campardo

IPC分类号： G11C1604

CPC分类号： G11C11/5621 ,  G11C8/14 ,  G11C11/56 ,  G11C16/08 ,  G11C16/30

摘要： A power supply circuit structure is useful with a row decoder for reading/writing data from/into memory cells of an integrated electrically programmable/erasable non-volatile memory device incorporating an array of multilevel memory cells. Advantageously, multiple supply voltages to the row decoder and a switching circuit for transferring the voltages over hierarchic-mode enabled conduction paths are provided.

摘要翻译： 电源电路结构对于包含多层存储器单元阵列的集成电可编程/可擦除非易失性存储器件的/从存储单元读/写数据的行解码器是有用的。 有利地，提供了对行解码器的多个电源电压和用于将电压传送到分层模式使能的传导路径的开关电路。

公开(公告)号：US06822905B2

公开(公告)日：2004-11-23

申请号：US10331106

申请日：2002-12-27

申请人： Rino Micheloni ,  Ilaria Motta

发明人： Rino Micheloni ,  Ilaria Motta

IPC分类号： G11C1606

CPC分类号： G11C16/30

摘要： A method and a circuit are for regulating the source terminal voltage of a non-volatile memory cell during the cell programming and/or reading phases. The method includes a phase of locally regulating the voltage value and includes comparing the source current of the cell array with a reference current. A fraction of the source current is converted to a voltage and compared with a voltage generated from a memory cell acting as a reference and being programmed to the distribution with the highest current levels. The comparison may be used for controlling a current generator to inject, into the source terminal, the current necessary to keep the predetermined voltage thereof at a constant value.

摘要翻译： 一种方法和电路用于在单元编程和/或读取阶段期间调节非易失性存储单元的源极端子电压。 该方法包括局部调节电压值的相位，并且包括将电池阵列的源电流与参考电流进行比较。 将源电流的一部分转换成电压，并将其与作为参考的存储器单元产生的电压进行比较，并将其编程为具有最高电流电平的分布。 比较可以用于控制电流发生器向源极端子注入将其预定电压保持在恒定值所需的电流。

公开(公告)号：US06728141B2

公开(公告)日：2004-04-27

申请号：US10123874

申请日：2002-04-16

申请人： Rino Micheloni ,  Giovanni Campardo

发明人： Rino Micheloni ,  Giovanni Campardo

IPC分类号： G11C700

CPC分类号： G11C7/062 ,  G11C7/04 ,  G11C7/22 ,  G11C11/56 ,  G11C11/5621 ,  G11C11/5642 ,  G11C16/28 ,  G11C16/32 ,  G11C2207/063 ,  G11C2211/5634

摘要： The method for timing reading of a memory cell envisages supplying the memory cell (with a constant current by means of a first capacitive element, integrating said current in a time interval, and controlling the duration of the time interval in such a way as to compensate for any deviations in the current from a nominal value. In particular, a reference current is supplied to a reference cell by means of a second capacitive element; next, a first voltage present on the second capacitive element is measured; finally, the memory cell is deactivated when the first voltage is equal to a second voltage, which is constant.

摘要翻译： 用于定时读取存储器单元的方法设想为存储器单元提供（通过第一电容元件的恒定电流，在时间间隔内积分所述电流，并以这样的方式来控制时间间隔的持续时间，以便补偿 特别是通过第二电容元件将参考电流提供给参考电池;接下来，测量存在于第二电容元件上的第一电压;最后，存储单元 当第一电压等于第二电压时，其被停用，该第二电压是恒定的。

公开(公告)号：US06643179B2

公开(公告)日：2003-11-04

申请号：US10047918

申请日：2002-01-14

申请人： Giovanni Campardo ,  Rino Micheloni

发明人： Giovanni Campardo ,  Rino Micheloni

IPC分类号： G11C1600

CPC分类号： G11C11/5621 ,  G11C7/067 ,  G11C11/56 ,  G11C11/5642 ,  G11C11/565 ,  G11C16/26

摘要： The method for reading a memory cell is based upon integration in time of the current supplied to the memory cell by a capacitive element. The capacitive element is initially charged and then discharged linearly in a preset time, while the memory cell is biased at a constant voltage. In a first operating mode, initially a first capacitor and a second capacitor are respectively charged to a first charge value and to a second charge value. The second capacitor is discharged through the memory cell at a constant current in a preset time; the first charge is shared between the first capacitor and the second capacitor; and then the shared charge is measured.

公开(公告)号：US06515911B2

公开(公告)日：2003-02-04

申请号：US09894975

申请日：2001-06-27

申请人： Giovanni Campardo ,  Rino Micheloni

发明人： Giovanni Campardo ,  Rino Micheloni

IPC分类号： G11C1606

CPC分类号： G11C16/0416 ,  G11C8/14

摘要： A circuit device structured to enable a hierarchic form of row decoding in semiconductor memory devices of the non-volatile type and including a matrix of memory cells with sectors organized into columns, wherein each sector has a group of local word lines individually connected to a main word line running through all of the matrix sectors which have rows in common is presented. The device includes a PMOS first transistor having conduction terminals connected respectively to the main word line and the local word line, an NMOS second transistor having conduction terminals connected respectively to the local word line and the main word line, and a PMOS third transistor having conduction terminals connected respectively to the main word line and the local word line. Such a third transistor is a charge transistor that reduces the charging time for the local word line.

摘要翻译： 一种电路装置，其被构造为能够实现非易失性类型的半导体存储器件中的行解码的分层形式，并且包括具有被组织成列的扇区的存储器单元的矩阵，其中每个扇区具有单独连接到主体的一组本地字线 提供了通过具有共同行的所有矩阵扇区的字线。 该器件包括具有分别连接到主字线和本地字线的导通端子的PMOS第一晶体管，具有分别连接到本地字线和主字线的导通端子的NMOS第二晶体管和具有导通的PMOS第三晶体管 端子分别连接到主字线和本地字线。 这样的第三晶体管是减少本地字线的充电时间的电荷晶体管。

公开(公告)号：US06456530B1

公开(公告)日：2002-09-24

申请号：US09602680

申请日：2000-06-26

申请人： Rino Micheloni ,  Matteo Zammattio ,  Giovanni Campardo

发明人： Rino Micheloni ,  Matteo Zammattio ,  Giovanni Campardo

IPC分类号： G11C1604

CPC分类号： G11C8/12 ,  G11C16/12

摘要： The memory device has hierarchical sector decoding. A plurality of groups of supply lines is provided, one for each sector row, extending parallel to the sector rows. A plurality of switching stages are each connected between a respective sector and a respective group of supply lines; the switching stages connected to sectors arranged on a same column are controlled by same control signals supplied on control lines extending parallel to the columns of sectors. For biasing the sectors, modification voltages are sent to at least one selected group of biasing lines, and control signals are sent to the switching stages connected to a selected sector column.

摘要翻译： 存储器件具有分级扇区解码。 提供多组供应管线，每个扇区行一个平行于扇区行延伸。 多个开关级各自连接在相应的扇区和相应的一组供电线之间; 连接到布置在同一列上的扇区的开关级由与扇区列平行延伸的控制线上提供的相同控制信号控制。 为了偏置扇区，修改电压被发送到至少一组选定的偏置线，并且控制信号被发送到连接到所选扇区列的切换级。

公开(公告)号：US06307396B1

公开(公告)日：2001-10-23

申请号：US09231130

申请日：1998-12-30

申请人： Jacopo Mulatti ,  Marco Maccarrone ,  Ignazio Martines ,  Rino Micheloni

发明人： Jacopo Mulatti ,  Marco Maccarrone ,  Ignazio Martines ,  Rino Micheloni

IPC分类号： H03K190185

CPC分类号： H03K19/0016

摘要： A low-consumption TTL-CMOS input buffer stage includes a chain of inverters cascade connected between an input receiving electric signals at a TTL logic level and an output reproducing electric signals at a CMOS logic level, and powered between a first or supply voltage reference and a second or ground reference. Advantageously, the first inverter in the chain includes a means of selecting the delivery path to the stage according to an activate signal for a low-consumption operation mode. In essence, the first inverter of the buffer has two signal paths: one for normal operation and the other for low consumption operation.

摘要翻译： 低功耗TTL-CMOS输入缓冲级包括串联的反相器链，其串联在接收TTL逻辑电平的电信号的输入端和CMOS逻辑电平的输出再现电信号之间，并且在第一或电源电压基准和 第二或地面参考。 有利地，链中的第一反相器包括根据低功耗操作模式的激活信号选择到载物台的输送路径的装置。 实质上，缓冲器的第一个反相器具有两个信号路径：一个用于正常操作，另一个用于低功耗操作。

公开(公告)号：US6094073A

公开(公告)日：2000-07-25

申请号：US432642

申请日：1999-11-02

申请人： Giovanni Campardo ,  Rino Micheloni ,  Stefano Commodaro

发明人： Giovanni Campardo ,  Rino Micheloni ,  Stefano Commodaro

IPC分类号： G11C8/10 ,  G11C16/12 ,  H03K19/082

CPC分类号： G11C8/10 ,  G11C16/12

摘要： The row decoder includes a predecoding stage supplied with row addresses and generating predecoding signals; and a final decoding stage, which, on the basis of the predecoding signals, drives the individual rows in the array. The predecoding stage includes a number of predecoding circuits presenting two parallel signal paths: a low-voltage path used in read mode, and a high-voltage path used in programming mode. A CMOS switch separates the two paths, is driven by high voltage via a voltage shifter in programming mode, and, being formed at predecoding level, involves no integration problems.

摘要翻译： 行解码器包括提供有行地址并产生预解码信号的预解码级; 以及最终解码阶段，其基于预解码信号驱动阵列中的各行。 预解码阶段包括多个预解码电路，其呈现两个并行信号路径：在读取模式中使用的低电压路径，以及在编程模式中使用的高压路径。 CMOS开关将两路径分开，通过编程模式下的电压转换器由高电压驱动，并且在预解码级别形成，不涉及集成问题。

公开(公告)号：US6075750A

公开(公告)日：2000-06-13

申请号：US186497

申请日：1998-11-04

申请人： Giovanni Campardo ,  Rino Micheloni ,  Marco Maccarrone ,  Matteo Zammattio

发明人： Giovanni Campardo ,  Rino Micheloni ,  Marco Maccarrone ,  Matteo Zammattio

IPC分类号： G11C8/18 ,  G11C8/00

CPC分类号： G11C8/18

摘要： A method and a circuit generate a pulse synchronization signal (ATD) for timing the memory cell read phase in semiconductor integrated electronic memory devices. The pulse signal (ATD) is generated upon detection of a change in logic state of at least one of a plurality of address input terminals of the memory cells. The method consists of duplicating the ATD signal into at least one pair of signals and propagating such signals through separate parallel timing chains at the ends of which the ATD signal is reinstated, the chains being alternately active.

摘要翻译： 一种方法和电路产生用于对半导体集成电子存储器件中的存储单元读取相位进行定时的脉冲同步信号（ATD）。 在检测到存储器单元的多个地址输入端中的至少一个的逻辑状态的变化时产生脉冲信号（ATD）。 该方法包括将ATD信号复制到至少一对信号中，并且通过在ATD信号被恢复的端部处的分离的并行定时链传播这样的信号，链条交替活跃。