公开(公告)号：US06891755B2

公开(公告)日：2005-05-10

申请号：US10340207

申请日：2003-01-10

申请人： Andrea Silvagni ,  Rino Micheloni ,  Giovanni Campardo

发明人： Andrea Silvagni ,  Rino Micheloni ,  Giovanni Campardo

IPC分类号： G11C16/08 ,  G11C16/04

CPC分类号： G11C16/08 ,  G11C2216/22

摘要： A memory device includes an array of memory cells organized into a plurality of sectors, and local wordlines and local bitlines are connected to the memory cells in each respective sector. Main read wordlines and main program wordlines are connected to the local wordlines in each sector. A main read row decoder is connected to the main read wordlines, and a main program row decoder connected to the main program wordlines. Main read bitlines and main program bitlines are connected to the local bitlines in each sector. A main read column decoder is connected to the main read bitlines, and a main program column decoder is connected to the main program wordlines. A read address bus is connected to the main read row decoder and to the main read column decoder for providing an address thereto. A program address bus is connected to the main read column decoder and to the main program row decoder for providing an address thereto.

摘要翻译： 存储器件包括组织成多个扇区的存储器单元的阵列，并且本地字线和本地位线连接到每个相应扇区中的存储器单元。 主读取字线和主程序字线连接到每个扇区中的本地字线。 主读取行解码器连接到主读取字线，连接到主程序字线的主程序行解码器。 主读位线和主程序位线连接到每个扇区中的本地位线。 主读取列解码器连接到主读取位线，主程序列解码器连接到主程序字线。 读地址总线连接到主读行解码器和主读列解码器，以提供地址。 程序地址总线连接到主读取列解码器和主程序行解码器，以向其提供地址。

公开(公告)号：US5793676A

公开(公告)日：1998-08-11

申请号：US649857

申请日：1996-05-03

申请人： Lorenzo Bedarida ,  Giovanni Campardo ,  Giuseppe Fusillo ,  Andrea Silvagni

发明人： Lorenzo Bedarida ,  Giovanni Campardo ,  Giuseppe Fusillo ,  Andrea Silvagni

IPC分类号： G11C8/12 ,  G11C16/08 ,  G11C11/34

CPC分类号： G11C8/12 ,  G11C16/08

摘要： A memory array is divided, at the design stage, into a plurality of elementary sectors; depending on the specific application and the requirements of the user, the elementary sectors are grouped into composite sectors of desired size and number; a correlating unit memorizes the correlation between each composite sector and the elementary sectors; and, to address a composite sector, the relative address is supplied to the correlating unit which provides for addressing the elementary sectors associated with the addressed composite sector on the basis of the memorized correlation table.

公开(公告)号：US5748528A

公开(公告)日：1998-05-05

申请号：US642813

申请日：1996-05-03

申请人： Giovanni Campardo ,  Lorenzo Bedarida ,  Giuseppe Fusillo ,  Andrea Silvagni

发明人： Giovanni Campardo ,  Lorenzo Bedarida ,  Giuseppe Fusillo ,  Andrea Silvagni

IPC分类号： G11C17/00 ,  G11C7/18 ,  G11C8/10 ,  G11C8/12 ,  G11C16/02 ,  G11C16/06 ,  G11C16/10 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/10 ,  G11C7/18 ,  G11C8/10 ,  G11C8/12 ,  G11C2216/22

摘要： A memory device having a memory array, a row decoding unit, a column decoding unit, and a control unit; the memory array presents global bit lines extending along the whole of the array and connected to respective local bit lines, one for each of the sectors; a switch is provided between the global bit lines and each respective local bit line to selectively connect a selected global bit line and only one of the associated local bit lines; and the switches are controlled by local decoding units over control lines, to address the sectors independently and so perform operations (read, erase, write) simultaneously in two different sectors in different rows and columns.

摘要翻译： 具有存储器阵列，行解码单元，列解码单元和控制单元的存储器件; 存储器阵列呈现沿整个阵列延伸并连接到相应的局部位线的全局位线，每个扇区一个; 在全局位线和每个相应的局部位线之间提供开关以选择性地连接所选择的全局位线和仅一个相关联的局部位线; 并且开关由控制线上的本地解码单元控制，以独立地寻址扇区，并且因此在不同行和列中的两个不同扇区中同时执行操作（读取，擦除，写入）。

公开(公告)号：US5949713A

公开(公告)日：1999-09-07

申请号：US94916

申请日：1998-06-15

申请人： Lorenzo Bedarida ,  Giovanni Campardo ,  Giuseppe Fusillo ,  Andrea Silvagni

发明人： Lorenzo Bedarida ,  Giovanni Campardo ,  Giuseppe Fusillo ,  Andrea Silvagni

IPC分类号： G11C8/12 ,  G11C16/08 ,  G11C11/34

CPC分类号： G11C8/12 ,  G11C16/08

摘要： A memory array is divided, at the design stage, into a plurality of elementary sectors; depending on the specific application and the requirements of the user, the elementary sectors are grouped into composite sectors of desired size and number; a correlating unit memorizes the correlation between each composite sector and the elementary sectors; and, to address a composite sector, the relative address is supplied to the correlating unit which provides for addressing the elementary sectors associated with the addressed composite sector on the basis of the memorized correlation table.

摘要翻译： 存储器阵列在设计阶段被划分成多个基本扇区; 取决于用户的具体应用和要求，基本扇区被分组成所需大小和数量的复合扇区; 相关单元记录每个复合扇区与基本扇区之间的相关性; 并且为了寻址复合扇区，将相对地址提供给相关单元，该相关单元基于存储的相关表来提供与寻址的复合扇区相关联的基本扇区的寻址。