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    Stacking Technique for Circuit Devices
    81.
    发明申请
    Stacking Technique for Circuit Devices 审中-公开
    电路器件堆叠技术

    公开(公告)号：US20110034045A1

    公开(公告)日：2011-02-10

    申请号：US12536854

    申请日：2009-08-06

    申请人： Christoph Bilger ,  Peter Gregorius ,  Michael Bruennert ,  Maurizio Skerlj ,  Wolfgang Walthes ,  Johannes Stecker ,  Hermann Ruckerbauer ,  Dirk Scheideler ,  Roland Barth

    发明人： Christoph Bilger ,  Peter Gregorius ,  Michael Bruennert ,  Maurizio Skerlj ,  Wolfgang Walthes ,  Johannes Stecker ,  Hermann Ruckerbauer ,  Dirk Scheideler ,  Roland Barth

    IPC分类号： H01R12/00 ,  H05K1/00

    CPC分类号： H01R31/06 ,  H01L25/105 ,  H01L2224/81141 ,  H01L2224/81191 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2225/1094 ,  H01R12/714 ,  H01R13/2421

    摘要： Stackable circuit devices include mechanical and electrical connection elements that are optionally disengageable and disconnectable. The mechanical connection elements comprise pairs of complementary male and female plug-in engagement elements respectively arranged at opposite matching positions on top and bottom faces of each device package. The male and female plug-in engagement elements provide a mutual plug-in engagement. The electrical connection elements comprise a plurality of first and second complementary contact elements respectively arranged in opposite and matching positions on either the top or bottom face of each device package. When the circuit devices are stacked, the first contact elements are respectively configured to provide an electrical connection to a complementary matching second contact element of an adjacently plugged in circuit device. Some of the stackable circuit devices may accommodate an integrated memory die or chip and others of the stackable circuit devices may include line routing and distribution blocks.

    摘要翻译： 可堆叠电路器件包括机械和电连接元件，其可任选地可分离和可断开。 机械连接元件包括分别布置在每个器件封装的顶面和底面上的相对匹配位置的成对的互补的凸形和阴插入接合元件。 男性和女性插入式接合元件提供相互插件接合。 电连接元件包括多个第一和第二互补触点元件，其分别布置在每个器件封装的顶面或底面上的相对位置和匹配位置。 当电路器件堆叠时，第一接触元件分别构造成提供与相邻插入电路器件的互补匹配的第二接触元件的电连接。 可堆叠电路设备中的一些可以容纳集成存储器管芯或芯片，并且可堆叠电路器件中的其他可以包括线路布线和分配块。

    METHOD FOR CONTROLLING A MEMORY MODULE AND MEMORY CONTROL UNIT
    82.
    发明申请
    METHOD FOR CONTROLLING A MEMORY MODULE AND MEMORY CONTROL UNIT 审中-公开
    用于控制存储器模块和存储器控制单元的方法

    公开(公告)号：US20090287957A1

    公开(公告)日：2009-11-19

    申请号：US12122300

    申请日：2008-05-16

    申请人： Christoph Bilger ,  Peter Gregorius ,  Michael Bruennert ,  Maurizio Skerlj ,  Wolfgang Walthes ,  Johannes Stecker ,  Hermann Ruckerbauer ,  Dirk Scheideler

    发明人： Christoph Bilger ,  Peter Gregorius ,  Michael Bruennert ,  Maurizio Skerlj ,  Wolfgang Walthes ,  Johannes Stecker ,  Hermann Ruckerbauer ,  Dirk Scheideler

    IPC分类号： G06F11/20

    CPC分类号： G11C29/70 ,  G11C5/04

    摘要： A memory control unit for controlling a memory module comprising a plurality of memory cells, said memory control unit comprising means for detecting failure of at least one memory cell, means for deactivating said at least one defective memory cell, means for assigning the address of said at least one defective memory cell to at least one replacement memory cell, first tracking means for tracking the remaining replacement memory cells and masking means to hide the address of a defective memory cell to prevent further usage of this address instead of assigning said address to a replacement memory cell.

    摘要翻译： 一种用于控制包括多个存储单元的存储器模块的存储器控​​制单元，所述存储器控制单元包括用于检测至少一个存储单元的故障的装置，用于停用所述至少一个有缺陷的存储器单元的装置，用于分配所述至少一个存储单元的地址的装置 至少一个有缺陷的存储器单元到至少一个替换存储器单元，用于跟踪剩余的替换存储器单元的第一跟踪装置和隐藏缺陷存储器单元的地址的掩蔽装置，以防止进一步使用该地址而不是将所述地址分配给 更换记忆体。

    METHOD AND APPARATUS FOR STORAGE DEVICE WITH A LOGIC UNIT AND METHOD FOR MANUFACTURING SAME
    84.
    发明申请
    METHOD AND APPARATUS FOR STORAGE DEVICE WITH A LOGIC UNIT AND METHOD FOR MANUFACTURING SAME 有权
    具有逻辑单元的存储装置的方法和装置及其制造方法

    公开(公告)号：US20090175100A1

    公开(公告)日：2009-07-09

    申请号：US11971819

    申请日：2008-01-09

    申请人： Christoph Bilger ,  Peter Gregorius ,  Michael Bruennert ,  Maurizio Skerlj ,  Wolfgang Walthes ,  Johannes Stecker ,  Hermann Ruckerbauer ,  Dirk Scheideler ,  Roland Barth

    发明人： Christoph Bilger ,  Peter Gregorius ,  Michael Bruennert ,  Maurizio Skerlj ,  Wolfgang Walthes ,  Johannes Stecker ,  Hermann Ruckerbauer ,  Dirk Scheideler ,  Roland Barth

    IPC分类号： G11C7/10

    CPC分类号： G11C7/1006

    摘要： Method and apparatus that relate to a storage device comprising a plurality of memory cells, an interface device configured to connect the storage device to a host system and configured to transmit signals to read and write data from the host system to the memory cells via a first and second data path, and a logic unit. The logic unit is configured to read and write data from the plurality of memory cells via the second data path, and configured to perform logic operations on data stored in the plurality of memory cells. When performing read and write operations, the first data path excludes the logic unit, and the second data path includes the logic unit. Furthermore, the logic unit is communicatively coupled between the interface device and the plurality of memory cells. Additionally, a method for manufacturing the memory device is provided.

    摘要翻译： 涉及包括多个存储器单元的存储设备的方法和设备，接口设备，被配置为将存储设备连接到主机系统，并且被配置为经由第一个存储器单元将数据从主机系统读取和写入到存储器单元 和第二数据路径，以及逻辑单元。 逻辑单元被配置为经由第二数据路径从多个存储器单元读取和写入数据，并且被配置为对存储在多个存储器单元中的数据执行逻辑运算。 当执行读和写操作时，第一数据路径排除逻辑单元，第二数据路径包括逻辑单元。 此外，逻辑单元通信地耦合在接口设备和多个存储器单元之间。 另外，提供了一种用于制造存储器件的方法。

    Data handover unit for transferring data between different clock domains by parallelly reading out data bits from a plurality of storage elements
    86.
    发明授权
    Data handover unit for transferring data between different clock domains by parallelly reading out data bits from a plurality of storage elements 有权
    数据切换单元，用于通过从多个存储元件并行读出数据位，在不同的时钟域之间传送数据

    公开(公告)号：US07461186B2

    公开(公告)日：2008-12-02

    申请号：US11346993

    申请日：2006-02-03

    申请人： Martin Streibl ,  Peter Gregorius ,  Ralf Schledz ,  Thomas Rickes ,  Zheng Gu

    发明人： Martin Streibl ,  Peter Gregorius ,  Ralf Schledz ,  Thomas Rickes ,  Zheng Gu

    IPC分类号： G06F13/38 ,  G06F11/00

    CPC分类号： G11C7/22 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093

    摘要： The invention provides a data handover unit for transferring data from a furst clock domain to a second clock domain, comprising: a first clock unit operable to supply a first clock signal; a selector stage operable to sample an incoming data stream with respect to the first clock signal; a second clock unit operable to supply a second clock signal; a storage unit coupled with the selector stage, wherein the storage unit has a first plurality of storage elements each of which is operable to store one bit of data of the sampled data stream, an output unit for parallelly reading out a fram of data from a second plurality of storage elements included in the first plurality of storage elements with respect to the second clock signal, wherein the selector stage is further operable to successively write the data bits of the sampled data stream into the first plurality of storage elements and to store the respective data bits of the sampled data stream in the respective storage elements until they were read out by the output unit.

    摘要翻译： 本发明提供一种用于将数据从第一时钟域传送到第二时钟域的数据切换单元，包括：第一时钟单元，用于提供第一时钟信号; 选择器级，可操作以相对于所述第一时钟信号对输入数据流进行采样; 第二时钟单元，用于提供第二时钟信号; 与所述选择器级耦合的存储单元，其中所述存储单元具有第一多个存储元件，每个存储元件可操作以存储所述采样数据流的一位数据;输出单元，用于从 第二多个存储元件相对于第二时钟信号包括在第一多个存储元件中，其中选择器级还可操作以将采样数据流的数据位连续地写入第一多个存储元件并存储 相应的存储元件中的采样数据流的相应数据位直到它们被输出单元读出。

    Clock and data recovery unit
    87.
    发明授权
    Clock and data recovery unit 失效
    时钟和数据恢复单元

    公开(公告)号：US07457391B2

    公开(公告)日：2008-11-25

    申请号：US10809122

    申请日：2004-03-25

    申请人： Peter Gregorius ,  Petyo Pentchev

    发明人： Peter Gregorius ,  Petyo Pentchev

    IPC分类号： H03D3/24

    CPC分类号： H03L7/07 ,  H03L7/0814 ,  H04L7/0025 ,  H04L7/0083 ,  H04L7/0337

    摘要： A clock and data recovery unit for recovering a received serial data bit stream having: phase adjustment means for adjustment of a sampling time in the center of a unit interval of the received data bit stream, wherein the phase adjustment means comprises means for generating equidistant reference phase signals, a phase interpolation unit, an oversampling unit, a serial-to-parallel-conversion unit, a binary phase detection unit, and a loop filter; and data recognition means for recovery of the received data stream which includes a number of parallel data recognition FIR-Filters, wherein each data recognition FIR-Filter comprises a weighting unit, a summing unit, and a comparator unit.

    摘要翻译： 一种用于恢复接收的串行数据比特流的时钟和数据恢复单元，具有：用于调整接收数据比特流的单位间隔中心的采样时间的相位调整装置，其中相位调整装置包括用于产生等距参考的装置 相位信号，相位插值单元，过采样单元，串并转换单元，二进制相位检测单元和环路滤波器; 以及用于恢复包括多个并行数据识别FIR滤波器的接收数据流的数据识别装置，其中每个数据识别FIR滤波器包括加权单元，加法单元和比较器单元。

    DATA RECEIVER WITH CLOCK RECOVERY CIRCUIT
    88.
    发明申请
    DATA RECEIVER WITH CLOCK RECOVERY CIRCUIT 有权
    具有时钟恢复电路的数据接收器

    公开(公告)号：US20070258552A1

    公开(公告)日：2007-11-08

    申请号：US11742577

    申请日：2007-04-30

    申请人： Martin Streibl ,  Peter Gregorius ,  Thomas Rickes ,  Ralf Schledz

    发明人： Martin Streibl ,  Peter Gregorius ,  Thomas Rickes ,  Ralf Schledz

    IPC分类号： H04L7/00

    CPC分类号： H04L7/0054 ,  G11C7/1078 ,  G11C7/1084 ,  H03L7/08 ,  H04L7/007

    摘要： A data receiver has a sampling unit connected to a data signal input and configured to sample a data signal amplitude and amplify the sampled data signal amplitude to a predetermined value, a sampling clock generator unit connected to the sampling unit and configured to predetermine a sampling clock for the sampling unit, an evaluation unit connected to the sampling unit and configured to determine the time duration required by the sampling unit for amplifying the sampled data signal amplitude to the predetermined value and evaluate the time duration determined, and a control unit connected to the evaluation unit and the sampling clock generator and configured to define the sampling clock on the basis of the evaluation of the time duration determined by the evaluation unit.

    摘要翻译： 数据接收机具有连接到数据信号输入端并被配置为采样数据信号振幅并将采样数据信号振幅放大到预定值的采样单元，采样时钟发生器单元连接到采样单元并被配置为预先确定采样时钟 对于采样单元，评估单元连接到采样单元并且被配置为确定采样单元需要的持续时间以将采样的数据信号幅度放大到预定值并评估所确定的持续时间，以及控制单元 评估单元和采样时钟发生器，并且被配置为基于由评估单元确定的持续时间的评估来定义采样时钟。

    Method and filter arrangement for digital recursive filtering in the time domain
    89.
    发明授权
    Method and filter arrangement for digital recursive filtering in the time domain 失效
    时域中数字递归滤波的方法和滤波器布置

    公开(公告)号：US07290022B2

    公开(公告)日：2007-10-30

    申请号：US10714811

    申请日：2003-11-17

    申请人： Heinz Mattes ,  Peter Gregorius ,  Paul Georg Lindt

    发明人： Heinz Mattes ,  Peter Gregorius ,  Paul Georg Lindt

    IPC分类号： G06F17/10

    CPC分类号： H03H17/0223 ,  H03H17/04

    摘要： A method and apparatus for fast digital filtering that requires only filter stages of first and second order. A desired rational filter transfer function is represented as a sum of first and second order intermediate transfer functions. A time dependent input signal is first fed in parallel into a plurality of first and second order intermediate recursive filter stages. Then, the outputs of the intermediate filter stages are summed up to an output filter signal that corresponds to the desired rational filter transfer function. The method and apparatus reduces the amount of calculational effort to the order of O(N), where N denotes the number of sampling points in the time domain, because the digital filtering is based on a discrete recursive convolution in the time domain.

    摘要翻译： 用于快速数字滤波的方法和装置，其仅需要一阶和二阶滤波器阶段。 期望的合理滤波传递函数被表示为第一和第二阶中间传递函数的和。 首先将依赖于时间的输入信号并入多个第一和第二阶中间递归滤波器级。 然后，将中间滤波器级的输出相加到对应于期望的有理滤波器传递函数的输出滤波器信号。 该方法和装置将计算努力的量减少到O（N）的阶数，其中N表示时域中的采样点的数量，因为数字滤波是基于时域中的离散递归卷积。

    Memory device having components for transmitting and receiving signals synchronously
    90.
    发明授权
    Memory device having components for transmitting and receiving signals synchronously 有权
    存储器件具有用于同步发送和接收信号的组件

    公开(公告)号：US07215597B2

    公开(公告)日：2007-05-08

    申请号：US11046160

    申请日：2005-01-28

    申请人： Peter Gregorius

    发明人： Peter Gregorius

    IPC分类号： G11C8/00

    CPC分类号： G11C7/1072 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093

    摘要： One embodiment of the present invention provides a memory device comprising an array of memory cells, a control logic for writing data to and reading data from the array of memory cells, the control logic comprising a first interface, an input/output section for exchanging data, address and control signals with a circuit external to the memory device, the input/output section comprising a second interface for sending signals to and receiving signals from the first interface of the control logic, and a synchronizing facility connected to the first interface of the control logic and to the second interface of the input/output section for synchronizing the first interface of the control logic and the second interface of the input/output section.

    摘要翻译： 本发明的一个实施例提供了一种存储器件，包括存储器单元阵列，用于将数据写入存储器单元阵列并从存储器单元阵列读取数据的控制逻辑，该控制逻辑包括第一接口，用于交换数据的输入/输出部分 ，具有存储器件外部电路的地址和控制信号，所述输入/输出部分包括用于向控制逻辑的第一接口发送信号并从其接收信号的第二接口，以及连接到控制逻辑的第一接口的同步设备 控制逻辑和输入/输出部分的第二接口，用于使控制逻辑的第一接口和输入/输出部分的第二接口同步。