公开(公告)号：US20140270005A1

公开(公告)日：2014-09-18

申请号：US14210246

申请日：2014-03-13

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku ,  George Alan Wiley ,  Chulkyu Lee ,  Joseph Cheung

IPC: H04L27/20

CPC classification number: H04L27/2071 ,  G06F13/4063 ,  G08C19/00 ,  H04B1/06 ,  H04B3/00 ,  H04L25/0272 ,  H04L25/0292 ,  H04L69/18

Abstract: A termination network for a receiver device is provided to support both D-PHY signaling and N-factorial signaling. The first end of each of a plurality dynamically configurable switches is coupled to a common node. A first end of each of a plurality of resistances is coupled to a second end of a corresponding switch. A plurality of terminals receive differential signals and each terminal is coupled to a corresponding second end of a resistance. Each of a plurality differential receivers is coupled between two terminals of the termination network, wherein a first differential receiver and a second differential receiver are coupled to the same two terminals, the first differential receiver is used when the differential signals use a first type of differential signal encoding, the second differential receiver is used when the differential signals use a second type of differential signal encoding.

Abstract translation: 提供用于接收机设备的终端网络以支持D-PHY信令和N阶因子信令。 多个动态可配置开关中的每一个的第一端耦合到公共节点。 多个电阻中的每一个的第一端耦合到相应开关的第二端。 多个端子接收差分信号，并且每个端子耦合到电阻的对应的第二端。 多个差分接收器中的每一个耦合在终端网络的两个终端之间，其中第一差分接收机和第二差分接收机耦合到相同的两个终端，当差分信号使用第一类型的差分时，使用第一差分接收机 信号编码时，当差分信号使用第二类型的差分信号编码时，使用第二差分接收机。

公开(公告)号：US20140254732A1

公开(公告)日：2014-09-11

申请号：US14199898

申请日：2014-03-06

Applicant: QUALCOMM INCORPORATED

Inventor： Shoichiro Sengoku ,  George Alan Wiley ,  Chulkyu Lee ,  Joseph Cheung

IPC: H04L7/033

CPC classification number: H04L7/033 ,  H03K5/1252 ,  H03K5/1534 ,  H04L7/0066 ,  H04L7/027 ,  H04L25/0272 ,  H04L25/14 ,  H04L25/49 ,  H04L25/4906 ,  H04L25/493

Abstract: A method for performing multi-wire signaling encoding is provided in which a clock signal is encoded within symbol transitions. A sequence of data bits is converted into a plurality of m transition numbers. Each transition number is converted into a sequential symbol number from a set of sequential symbol numbers. The sequential symbol number is converted into a raw symbol that can be transmitted over a plurality of differential drivers. The raw symbol is transmitted spread over a plurality of n wires, wherein the clock signal is effectively embedded in the transmission of raw symbols since the conversion from transition number into a sequential symbol number guarantees that no two consecutive raw symbols are the same. The raw symbol is guaranteed to have a non-zero differential voltage across all pairs of the plurality of n wires.

Abstract translation: 提供了一种用于执行多线信令编码的方法，其中在符号转换内对时钟信号进行编码。 数据位序列被转换成多个m个转换数。 每个转换编号从一组顺序符号编号转换成顺序符号。 顺序符号号被转换成可以通过多个差分驱动器发送的原始符号。 原始符号被传播扩展到多条n线，其中时钟信号被有效地嵌入到原始符号的传输中，因为从转换数转换为顺序符号，从而确保没有两个连续的原始符号相同。 原始符号保证在多条n线的所有对上具有非零的差分电压。

公开(公告)号：US20130181742A1

公开(公告)日：2013-07-18

申请号：US13785174

申请日：2013-03-05

Applicant: QUALCOMM Incorporated

Inventor： Chulkyu Lee ,  Harry H. Dang ,  Abhay S. Dixit

IPC: H03K19/096 ,  G06F17/50 ,  H03K19/20

CPC classification number: H03K19/096 ,  G06F17/50 ,  H03K19/20 ,  H03M9/00

Abstract: A method includes applying a clock signal having an uneven duty cycle to a control input of at least one selection element of a selection circuit having a tree structure that includes multiple selection elements. The tree structure includes a data input tier and a data output tier.

Abstract translation: 一种方法包括将具有不均匀占空比的时钟信号应用于具有包括多个选择元件的树结构的选择电路的至少一个选择元件的控制输入。 树结构包括数据输入层和数据输出层。