公开(公告)号：US09639499B2

公开(公告)日：2017-05-02

申请号：US14302359

申请日：2014-06-11

申请人： QUALCOMM Incorporated

发明人： Shoichiro Sengoku ,  George Alan Wiley ,  Joseph Cheung

IPC分类号： G06F13/42 ,  G06F13/364 ,  H04L7/033

CPC分类号： G06F13/4291 ,  G06F13/364 ,  G06F13/4282 ,  G06F13/4295 ,  H04L7/0331

摘要： System, methods and apparatus are described that offer improved performance of a serial bus used for Inter-Integrated Circuit (I2C) and/or camera control interface (CCI) operations. CCI extension (CCIe) devices are described. CCIe devices may be configured as a bus master or as a slave. In one method, a CCIe transmitter may generate a transition number from a set of bits, convert the transition number into a sequence of symbols, and transmit the sequence of symbols in the signaling state of a two-wire serial bus. Timing information may be encoded in the transitions between symbols of consecutive pairs of symbols in the sequence of symbols. For example, each transition may cause a change in the signaling state of at least one wire of the two-wire serial bus. A CCIe receiver may derive a receive clock from the transitions in order to receive and decode the sequence of symbols.

公开(公告)号：US09337997B2

公开(公告)日：2016-05-10

申请号：US14199898

申请日：2014-03-06

申请人： QUALCOMM Incorporated

发明人： Shoichiro Sengoku ,  George Alan Wiley ,  Chulkyu Lee ,  Joseph Cheung

IPC分类号： H04L27/00 ,  H04L7/033 ,  H04L7/027 ,  H04L7/00 ,  H04L25/49 ,  H04L25/493 ,  H03K5/1252 ,  H03K5/1534 ,  H04L25/14 ,  H04L25/02

CPC分类号： H04L7/033 ,  H03K5/1252 ,  H03K5/1534 ,  H04L7/0066 ,  H04L7/027 ,  H04L25/0272 ,  H04L25/14 ,  H04L25/49 ,  H04L25/4906 ,  H04L25/493

摘要： A method for performing multi-wire signaling encoding is provided in which a clock signal is encoded within symbol transitions. A sequence of data bits is converted into a plurality of m transition numbers. Each transition number is converted into a sequential symbol number from a set of sequential symbol numbers. The sequential symbol number is converted into a raw symbol that can be transmitted over a plurality of differential drivers. The raw symbol is transmitted spread over a plurality of n wires, wherein the clock signal is effectively embedded in the transmission of raw symbols since the conversion from transition number into a sequential symbol number guarantees that no two consecutive raw symbols are the same. The raw symbol is guaranteed to have a non-zero differential voltage across all pairs of the plurality of n wires.

摘要翻译： 提供了一种用于执行多线信令编码的方法，其中在符号转换内对时钟信号进行编码。 数据位序列被转换成多个m个转换数。 每个转换编号从一组顺序符号编号转换成顺序符号。 顺序符号号被转换成可以通过多个差分驱动器发送的原始符号。 原始符号被传播扩展到多条n线，其中时钟信号被有效地嵌入在原始符号的传输中，因为从转换数转换为顺序符号，保证没有两个连续的原始符号相同。 原始符号保证在多条n线的所有对上具有非零的差分电压。

公开(公告)号：US20140270026A1

公开(公告)日：2014-09-18

申请号：US14205242

申请日：2014-03-11

申请人： QUALCOMM Incorporated

发明人： Shoichiro Sengoku ,  George Alan Wiley ,  Joseph Cheung

IPC分类号： H04L7/027

CPC分类号： H04L7/027 ,  G06F13/4072 ,  G06F13/4295 ,  H04L25/00 ,  H04L25/14

摘要： System, methods and apparatus are described that facilitate transmission of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. A sequence of data bits is converted into M transition numbers, which are then converted into a sequence of symbols. The sequence of symbols is transmitted received over N wires. A clock signal may be effectively embedded in the transmission of the sequence of symbols. Each of the sequence of symbols may be selected based on a corresponding one of the M transition numbers and a value of a preceding one of the sequence of symbols.

摘要翻译： 描述了便于通过多线数据通信链路，特别是在电子设备内的两个设备之间传输数据的系统，方法和装置。 数据比特序列被转换成M个转换号码，然后转换成符号序列。 通过N线接收符号序列。 可以有效地将时钟信号嵌入到符号序列的传输中。 符号序列中的每一个可以基于M个转移号码中的一个和符号序列中的前一个的值来选择。

公开(公告)号：US09444612B2

公开(公告)日：2016-09-13

申请号：US14834219

申请日：2015-08-24

申请人： QUALCOMM Incorporated

发明人： Shoichiro Sengoku ,  George Alan Wiley ,  Joseph Cheung

IPC分类号： H04L7/00 ,  H04L7/027 ,  G06F13/40 ,  G06F13/42 ,  H04L25/14 ,  H04L25/00

CPC分类号： H04L7/027 ,  G06F13/4072 ,  G06F13/4295 ,  H04L25/00 ,  H04L25/14

摘要： System, methods and apparatus are described that facilitate transmission of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. A sequence of data bits is converted into M transition numbers, which are then converted into a sequence of symbols. The sequence of symbols is transmitted received over N wires. A clock signal may be effectively embedded in the transmission of the sequence of symbols. Each of the sequence of symbols may be selected based on a corresponding one of the M transition numbers and a value of a preceding one of the sequence of symbols.

公开(公告)号：US20160127121A1

公开(公告)日：2016-05-05

申请号：US14992450

申请日：2016-01-11

申请人： QUALCOMM Incorporated

发明人： Shoichiro Sengoku ,  George Alan Wiley ,  Chulkyu Lee ,  Joseph Cheung

IPC分类号： H04L7/027 ,  H04L25/493 ,  H04L25/02

CPC分类号： H04L7/033 ,  H03K5/1252 ,  H03K5/1534 ,  H04L7/0066 ,  H04L7/027 ,  H04L25/0272 ,  H04L25/14 ,  H04L25/49 ,  H04L25/4906 ,  H04L25/493

摘要： A method for performing multi-wire signaling encoding is provided in which a clock signal is encoded within symbol transitions. A sequence of data bits is converted into a plurality of m transition numbers. Each transition number is converted into a sequential number from a set of sequential numbers. The sequential number is converted into a raw symbol that can be transmitted over a plurality of differential drivers. The raw symbol is transmitted spread over a plurality of n wires, wherein the clock signal is effectively embedded in the transmission of raw symbols since the conversion from transition number into a sequential number guarantees that no two consecutive raw symbols are the same. The raw symbol is guaranteed to have a non-zero differential voltage across all pairs of the plurality of n wires.

摘要翻译： 提供了一种用于执行多线信令编码的方法，其中在符号转换内对时钟信号进行编码。 数据位序列被转换成多个m个转换数。 每个转换号码都从一组连续号码转换为一个顺序号码。 顺序号被转换成可以通过多个差分驱动器发送的原始符号。 原始符号被传播分散在多条n线上，其中时钟信号被有效地嵌入在原始符号的传输中，因为从转换数转换为序列号可保证没有两个连续的原始符号相同。 原始符号保证在多条n线的所有对上具有非零差分电压。

公开(公告)号：US09071220B2

公开(公告)日：2015-06-30

申请号：US13832990

申请日：2013-03-15

申请人： QUALCOMM Incorporated

发明人： Shoichiro Sengoku ,  George Alan Wiley ,  Chulkyu Lee ,  Joseph Cheung

IPC分类号： H03K17/16 ,  H03H2/00 ,  H04B1/04 ,  H04L25/02 ,  H04L25/14

CPC分类号： H03H2/005 ,  H04B1/04 ,  H04L25/0272 ,  H04L25/0278 ,  H04L25/14 ,  Y02D30/30

摘要： A termination network circuit for a differential signal transmitter comprises a plurality of n resistance elements and a plurality of differential signal drivers. A first end of each of the resistance elements is coupled at a common node, where n is an integer value and is the number of conductors used to transmit a plurality of differential signals. Each differential signal driver may include a positive terminal driver and a negative terminal driver. The positive terminal driver is coupled to a second end of a first resistance element while the negative terminal driver is coupled to a second end of a second resistance element. The positive terminal driver and the negative terminal driver are separately and independently switchable to provide a current having a magnitude and direction. During a transmission cycle each of the resistance elements has a current of a different magnitude and/or direction than the other resistance elements.

摘要翻译： 用于差分信号发射机的终端网络电路包括多个n个电阻元件和多个差分信号驱动器。 每个电阻元件的第一端在公共节点处耦合，其中n是整数值，并且是用于发送多个差分信号的导体的数量。 每个差分信号驱动器可以包括正极端子驱动器和负极端子驱动器。 正端子驱动器耦合到第一电阻元件的第二端，而负端子驱动器耦合到第二电阻元件的第二端。 正极端子驱动器和负极端子驱动器分别独立地切换以提供具有幅度和方向的电流。 在传输周期期间，每个电阻元件具有与其它电阻元件不同的幅度和/或方向的电流。

公开(公告)号：US20140372642A1

公开(公告)日：2014-12-18

申请号：US14302359

申请日：2014-06-11

申请人： QUALCOMM Incorporated

发明人： Shoichiro Sengoku ,  George Alan Wiley ,  Joseph Cheung

IPC分类号： G06F13/42

CPC分类号： G06F13/4291 ,  G06F13/364 ,  G06F13/4282 ,  G06F13/4295 ,  H04L7/0331

摘要： System, methods and apparatus are described that offer improved performance of a serial bus used for Inter-Integrated Circuit (I2C) and/or camera control interface (CCI) operations. CCI extension (CCIe) devices are described. CCIe devices may be configured as a bus master or as a slave. In one method, a CCIe transmitter may generate a transition number from a set of bits, convert the transition number into a sequence of symbols, and transmit the sequence of symbols in the signaling state of a two-wire serial bus. Timing information may be encoded in the transitions between symbols of consecutive pairs of symbols in the sequence of symbols. For example, each transition may cause a change in the signaling state of at least one wire of the two-wire serial bus. A CCIe receiver may derive a receive clock from the transitions in order to receive and decode the sequence of symbols.

公开(公告)号：US11006127B2

公开(公告)日：2021-05-11

申请号：US16588818

申请日：2019-09-30

申请人： QUALCOMM INCORPORATED

发明人： Meghal Varia ,  Serag Gadelrab ,  Wesley James Holland ,  Joseph Cheung ,  Dam Backer ,  Tom Longo

IPC分类号： H04N19/162 ,  H04N19/167 ,  H04N19/174 ,  H04N19/115 ,  H04N19/119 ,  G06F12/02 ,  H04N19/12 ,  H04N19/172 ,  H04N19/46 ,  H04N5/917

摘要： An exemplary method for intelligent compression uses a foveated-compression approach. First, the location of a fixation point within an image frame is determined. Next, the image frame is sectored into two or more sectors such that one of the two or more sectors is designated as a fixation sector and the remaining sectors are designated as foveation sectors. A sector may be defined by one or more tiles within the image frame. The fixation sector includes the particular tile that contains the fixation point and is compressed according to a lossless compression algorithm. The foveation sectors are compressed according to lossy compression algorithms. As the locations of foveation sectors increase in angular distance from the location of the fixation sector, a compression factor may be increased.

公开(公告)号：US09811499B2

公开(公告)日：2017-11-07

申请号：US15486217

申请日：2017-04-12

申请人： QUALCOMM Incorporated

发明人： Shoichiro Sengoku ,  George Alan Wiley ,  Joseph Cheung

IPC分类号： G06F13/42 ,  G06F13/364

CPC分类号： G06F13/4291 ,  G06F13/364 ,  G06F13/4282 ,  G06F13/4295 ,  H04L7/0331

摘要： System, methods and apparatus are described that offer improved performance of a serial bus used for Inter-Integrated Circuit (I2C) and/or camera control interface (CCI) operations. Other described devices may be configured as a bus master or as a slave. In one method, a transmitter may generate a transition number from a set of bits, convert the transition number into a sequence of symbols, and transmit the sequence of symbols in the signaling state of a two-wire serial bus. Timing information may be encoded in the transitions between symbols of consecutive pairs of symbols in the sequence of symbols. For example, each transition may cause a change in the signaling state of at least one wire of the two-wire serial bus. A receiver may derive a receive clock from the transitions in order to receive and decode the sequence of symbols.

公开(公告)号：US09582457B2

公开(公告)日：2017-02-28

申请号：US14302365

申请日：2014-06-11

申请人： QUALCOMM Incorporated

发明人： Shoichiro Sengoku ,  George Alan Wiley ,  Joseph Cheung

IPC分类号： G06F13/42 ,  G06F13/364 ,  H04L7/033

CPC分类号： G06F13/4291 ,  G06F13/364 ,  G06F13/4282 ,  G06F13/4295 ,  H04L7/0331

摘要： System, methods and apparatus are described that include a serial bus, including a serial bus used for Inter-Integrated Circuit (I2C) and/or camera control interface (CCI) operations. The bus has a first line and a second line, a first set of devices coupled to the bus and a second set of devices coupled to the bus. A method of operating the bus includes configuring the first set of devices to use the first line for data transmissions and use the second line for a first clock signal in a first mode of operation, and configuring the second set of devices to use both the first line and the second line for data transmissions while embedding a second clock signal within symbol transitions of the data transmissions in a second mode of operation.

摘要翻译： 描述了包括串行总线的系统，方法和装置，其包括用于互联集成电路（I2C）和/或相机控制接口（CCI）操作的串行总线。 总线具有第一线路和第二线路，耦合到总线的第一组设备和耦合到总线的第二组设备。 操作总线的方法包括配置第一组设备以使用第一行进行数据传输，并且在第一操作模式中使用第二行作为第一时钟信号，并且将第二组设备配置为使用第一组 线和用于数据传输的第二行，同时在第二操作模式中将第二时钟信号嵌入在数据传输的符号转换内。