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    C-PHY receiver equalization
    1.
    发明授权
    C-PHY receiver equalization 有权

    公开(公告)号：US10454725B1

    公开(公告)日：2019-10-22

    申请号：US16144582

    申请日：2018-09-27

    Applicant: QUALCOMM Incorporated

    Inventor： Chulkyu Lee ,  Jae Min Shin ,  George Alan Wiley

    IPC: H04L25/03 ,  H04L25/49 ,  H04B3/54 ,  G06F13/38

    Abstract: Methods, apparatus, and systems for data communication over a multi-wire, multi-phase interface are disclosed. A method includes equalizing three-phase signals received from two wires of the interface to provide equalized signals, providing first and second difference signals by comparing voltage differences between the equalized signals with first and second reference voltage levels respectively, capturing delayed and undelayed versions of the second difference signal using flipflops triggered by different edges in the first difference signal, and adjusting an equalizing circuit until outputs of the first flipflops indicate that a ratio of low-frequency attenuation to high-frequency amplification has been achieved that enables information to be accurately decoded from the three-phase signals. The three-phase signal received from a first of the two wires is in a different phase than the three-phase signal received from a second of the two wires.

    UNIFIED SYSTEMS AND METHODS FOR INTERCHIP AND INTRACHIP NODE COMMUNICATION
    3.
    发明申请
    UNIFIED SYSTEMS AND METHODS FOR INTERCHIP AND INTRACHIP NODE COMMUNICATION 审中-公开
    用于INTERCHIP和INTRACHIP节点通信的统一系统和方法

    公开(公告)号：US20170075843A1

    公开(公告)日：2017-03-16

    申请号：US14850104

    申请日：2015-09-10

    Applicant: QUALCOMM Incorporated

    Inventor： Richard Dominic Wietfeldt ,  Maxime Leclercq ,  George Alan Wiley

    IPC: G06F13/40

    CPC classification number: G06F13/4027 ,  G06F13/385 ,  G06F13/4068 ,  H04L43/0817

    Abstract: Unified systems and methods for interchip and intrachip node communication are disclosed. In one aspect, a single unified low-speed bus is provided that connects each of the chips within a computing device. The chips couple to the bus through a physical layer interface and associated gateway. The gateway includes memory that stores a status table summarizing statuses for every node in the interface fabric. As nodes experience state changes, the nodes provide updates to associated local gateways. The local gateways then message, using a scout message, remote gateways with information relating to the state changes. When a first node is preparing a signal to a second node, the first node checks the status table at the associated local gateway to determine a current status for the second node. Based on the status of the second node, the first node may send the message or take other appropriate action.

    Abstract translation: 公开了用于芯片间和节点间通信的统一系统和方法。 在一个方面，提供了连接计算设备内的每个芯片的单个统一的低速总线。 芯片通过物理层接口和相关网关耦合到总线。 网关包括存储状态表的内存，其汇总接口结构中每个节点的状态。 当节点经历状态改变时，节点向相关联的本地网关提供更新。 然后，本地网关使用侦察器消息来发送具有与状态改变有关的信息的远程网关。 当第一节点准备到第二节点的信号时，第一节点检查相关联的本地网关处的状态表以确定第二节点的当前状态。 基于第二节点的状态，第一节点可以发送消息或采取其他适当的动作。

    Low-power mode signal bridge for optical media
    4.
    发明授权
    Low-power mode signal bridge for optical media 有权
    用于光学介质的低功率模式信号桥

    公开(公告)号：US09584227B2

    公开(公告)日：2017-02-28

    申请号：US14802408

    申请日：2015-07-17

    Applicant: QUALCOMM Incorporated

    Inventor： George Alan Wiley

    IPC: H04B10/80 ,  H04L29/06

    CPC classification number: H04B10/801 ,  G06F13/387 ,  G06F13/4045 ,  H04L69/08 ,  H04L69/18 ,  Y02D10/14 ,  Y02D10/151

    Abstract: System, methods and apparatus are described that facilitate transmission of data between two devices. A data transfer method includes receiving first data from a first interface, the first data being received in signaling transmitted by a first device according to a first protocol, determining a mode of operation for a communication link to be used for transmitting the first data to a second device, transmitting the first data to the second device over an optical path of the communication link in a first mode of operation, transmitting the first data in accordance with the first protocol to the second device over an electrical path of the communication link in a second mode of operation, and in a third mode of operation, translating the first data to obtain second data, and transmitting the second data in accordance with a second protocol to the second device over the electrical path.

    Abstract translation: 描述了促进两个设备之间的数据传输的系统，方法和装置。 数据传输方法包括从第一接口接收第一数据，第一数据是按照第一协议由第一设备发送的信令中接收的，确定用于将第一数据发送到第一数据的通信链路的操作模式 第二设备，以第一操作模式通过通信链路的光路将第一数据发送到第二设备，根据第一协议，通过通信链路的电路径将第一数据发送到第二设备 第二操作模式，并且在第三操作模式中，转换第一数据以获得第二数据，以及根据第二协议将第二数据通过电路径发送到第二设备。

    TIME BASED EQUALIZATION FOR A C-PHY 3-PHASE TRANSMITTER
    5.
    发明申请
    TIME BASED EQUALIZATION FOR A C-PHY 3-PHASE TRANSMITTER 有权
    基于时间均衡的C-PHY三相发射机

    公开(公告)号：US20170026083A1

    公开(公告)日：2017-01-26

    申请号：US14808272

    申请日：2015-07-24

    Applicant: QUALCOMM Incorporated

    Inventor： Dhaval Sejpal ,  Chulkyu Lee ,  George Alan Wiley

    IPC: H04B3/54 ,  H04B3/462

    CPC classification number: H04B3/54 ,  H04B3/462 ,  H04L7/0087 ,  H04L7/033 ,  H04L25/0286 ,  H04L25/14 ,  H04L25/4917

    Abstract: A method, an apparatus, and a computer program product for data communication over a multi-wire, multi-phase interface are provided. The method may include providing a sequence of symbols to be transmitted on a 3-wire interface, each symbol in the sequence of symbols defining one of three voltage states for each wire of the 3-wire interface, driving all wires of the 3-wire interface to a common voltage state during a transition from a first transmitted symbol to a second transmitted symbol, driving each wire of the 3-wire interface in accordance with the second transmitted symbol after a predetermined delay. Each wire may be in a different voltage state from the other wires of the 3-wire interface during transmission of the each symbol. The common voltage state may lie between two of the three voltage states.

    Abstract translation: 提供了一种用于通过多线，多相接口进行数据通信的方法，装置和计算机程序产品。 该方法可以包括提供要在3线接口上发送的符号序列，符号序列中的每个符号定义3线接口的每根线的三种电压状态之一，驱动3线的所有线 在从第一传输符号到第二传输符号的转变期间接合到公共电压状态，在预定延迟之后根据第二传输符号驱动3线接口的每条线。 在每个符号的传输期间，每根导线可能处于与3线接口的其它线不同的电压状态。 公共电压状态可以位于三个电压状态中的两个之间。

    Adaptation to 3-phase signal swap within a trio
    6.
    发明授权
    Adaptation to 3-phase signal swap within a trio 有权
    适应三相三相信号互换

    公开(公告)号：US09520988B1

    公开(公告)日：2016-12-13

    申请号：US14817934

    申请日：2015-08-04

    Applicant: QUALCOMM Incorporated

    Inventor： George Alan Wiley ,  Ohjoon Kwon

    IPC: H04L7/00 ,  H04L27/20 ,  H04L27/227 ,  H04B1/40

    CPC classification number: H04L7/0087 ,  H04B1/40 ,  H04L7/0083 ,  H04L25/14 ,  H04L25/4923 ,  H04L27/0002 ,  H04L27/20 ,  H04L27/227

    Abstract: Systems, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Two Integrated Circuit (IC) devices may be collocated in an electronic apparatus and communicatively coupled through a 3-wire, 3-phase interface. A data transfer method operational on a first of the two or more devices includes determining presence of a misalignment of the 3-wire communication link involving two or more wires, and inverting a first bit of a 3-bit symbol encoded in a transition of signaling state of the 3-wire communication link when the misalignment of the 3-wire communication link is determined to affect phase relationships between two or more signals carried on the three wires, such that inverting the first bit corrects the phase relationships between the two or more signals. A version of the 3-phase signal may be communicated in a different phase state through each of three wires.

    Abstract translation: 描述了促进数据传输的系统，方法和装置，特别是在电子设备内的两个设备之间。 两个集成电路（IC）器件可以并置在电子设备中并且通过3线，3相接口通信耦合。 在两个或更多个设备中的第一个上可操作的数据传输方法包括确定存在涉及两条或更多条导线的3线通信链路的未对准，并且反转信令转换中编码的3位符号的第一位 当确定3线通信链路的未对准被确定为影响在三条线路上承载的两个或更多个信号之间的相位关系时，3线通信链路的状态，使得反转第一比特校正两个或更多个之间的相位关系 信号。 三相信号的版本可以通过三条线中的每一条在不同的相位状态下传送。

    Three phase and polarity encoded serial interface
    7.
    发明授权
    Three phase and polarity encoded serial interface 有权

    公开(公告)号：US09455850B2

    公开(公告)日：2016-09-27

    申请号：US14796207

    申请日：2015-07-10

    Applicant: QUALCOMM Incorporated

    Inventor： George Alan Wiley

    IPC: H04L25/34 ,  H04L25/49 ,  H04L27/22 ,  H04L5/20 ,  H04L25/02

    CPC classification number: H04L25/4917 ,  H04L5/20 ,  H04L7/033 ,  H04L25/0272 ,  H04L25/0282 ,  H04L25/0294 ,  H04L25/0298 ,  H04L27/22

    Abstract: A high speed serial interface is provided. In one aspect, the high speed serial interface uses three phase modulation for jointly encoding data and clock information. Accordingly, the need for de-skewing circuitry at the receiving end of the interface is eliminated, resulting in reduced link start-up time and improved link efficiency and power consumption. In one embodiment, the high speed serial interface uses fewer signal conductors than conventional systems having separate conductors for data and clock information. In another embodiment, the serial interface allows for data to be transmitted at any speed without the receiving end having prior knowledge of the transmission data rate. In another aspect, the high speed serial interface uses polarity encoded three phase modulation for jointly encoding data and clock information. This further increases the link capacity of the serial interface by allowing for more than one bit to be transmitted in any single baud interval.

    LINE-MULTIPLEXED UART
    9.
    发明申请
    LINE-MULTIPLEXED UART 有权
    线路多路复用UART

    公开(公告)号：US20160246570A1

    公开(公告)日：2016-08-25

    申请号：US14631078

    申请日：2015-02-25

    Applicant: QUALCOMM Incorporated

    Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt ,  George Alan Wiley

    IPC: G06F5/16 ,  G06F5/06 ,  G06F1/12 ,  G06F13/40 ,  G06F13/16

    CPC classification number: G06F5/16 ,  G06F1/12 ,  G06F5/065 ,  G06F13/1673 ,  G06F13/385 ,  G06F13/4022

    Abstract: A line multiplexed UART interface is provided that multiplexes a UART transmit and CTS functions on a transmit pin and that multiplexes a UART receive and RTS functions on a receive pin. In this fashion, the conventional need for an additional RTS pin and an additional CTS pin is obviated such that the line multiplexed UART interface uses just the transmit pin and the receive pin.

    Abstract translation: 提供了一种线路复用UART接口，可在发送引脚上复用UART发送和CTS功能，并在接收引脚上复用UART接收和RTS功能。 以这种方式，消除了额外的RTS引脚和附加CTS引脚的常规需求，使得线路复用UART接口仅使用发送引脚和接收引脚。

    TRANSCODING METHOD FOR MULTI-WIRE SIGNALING THAT EMBEDS CLOCK INFORMATION IN TRANSITION OF SIGNAL STATE
    10.
    发明申请
    TRANSCODING METHOD FOR MULTI-WIRE SIGNALING THAT EMBEDS CLOCK INFORMATION IN TRANSITION OF SIGNAL STATE 有权
    用于信号转换时钟信号的多线信号的扫描方法

    公开(公告)号：US20160127121A1

    公开(公告)日：2016-05-05

    申请号：US14992450

    申请日：2016-01-11

    Applicant: QUALCOMM Incorporated

    Inventor： Shoichiro Sengoku ,  George Alan Wiley ,  Chulkyu Lee ,  Joseph Cheung

    IPC: H04L7/027 ,  H04L25/493 ,  H04L25/02

    CPC classification number: H04L7/033 ,  H03K5/1252 ,  H03K5/1534 ,  H04L7/0066 ,  H04L7/027 ,  H04L25/0272 ,  H04L25/14 ,  H04L25/49 ,  H04L25/4906 ,  H04L25/493

    Abstract: A method for performing multi-wire signaling encoding is provided in which a clock signal is encoded within symbol transitions. A sequence of data bits is converted into a plurality of m transition numbers. Each transition number is converted into a sequential number from a set of sequential numbers. The sequential number is converted into a raw symbol that can be transmitted over a plurality of differential drivers. The raw symbol is transmitted spread over a plurality of n wires, wherein the clock signal is effectively embedded in the transmission of raw symbols since the conversion from transition number into a sequential number guarantees that no two consecutive raw symbols are the same. The raw symbol is guaranteed to have a non-zero differential voltage across all pairs of the plurality of n wires.

    Abstract translation: 提供了一种用于执行多线信令编码的方法，其中在符号转换内对时钟信号进行编码。 数据位序列被转换成多个m个转换数。 每个转换号码都从一组连续号码转换为一个顺序号码。 顺序号被转换成可以通过多个差分驱动器发送的原始符号。 原始符号被传播分散在多条n线上，其中时钟信号被有效地嵌入在原始符号的传输中，因为从转换数转换为序列号可保证没有两个连续的原始符号相同。 原始符号保证在多条n线的所有对上具有非零差分电压。

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