公开(公告)号：US10600737B2

公开(公告)日：2020-03-24

申请号：US15722703

申请日：2017-10-02

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Pascal Fornara ,  Jean-Philippe Escales

IPC: H01L21/31 ,  H01L23/532 ,  H01L21/768 ,  H01L21/02 ,  H01L23/522 ,  H01L23/528

Abstract: A non-porous dielectric barrier is provided between a porous portion of a dielectric region and an electrically conductive element of an interconnect portion of an integrated circuit. This non-porous dielectric barrier protects the integrated circuit from breakdown of the least one dielectric region caused by electrical conduction assisted by the presence of defects located in the at least one dielectric region.

公开(公告)号：US10593772B2

公开(公告)日：2020-03-17

申请号：US16036240

申请日：2018-07-16

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Julien Delalleau

IPC: H01L29/423 ,  H01L27/11521 ,  H01L29/788 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66 ,  H01L27/11524

Abstract: A MOS transistor located in and on a semiconductor substrate has a drain region, a source region and a conductive gate region. The conductive gate region includes a first conductive gate region that is insulated from the semiconductor substrate and a second conductive gate region that is insulated from and located above the first conductive gate region. A length of the first conductive gate region, measured in the drain-source direction, is greater than a length of the second conductive gate region, also measured in the drain-source direction. The first conductive gate region protrudes longitudinally in the drain-source direction beyond the second conductive gate region at least on one side of the second conductive gate region so as to extend over at least one of the source and drain regions.

公开(公告)号：US20190172785A1

公开(公告)日：2019-06-06

申请号：US16270356

申请日：2019-02-07

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara ,  Christian Rivero

IPC: H01L23/525 ,  H01L21/768 ,  H01L23/522

Abstract: An integrated circuit includes a substrate; an interconnect portion disposed over the substrate, the interconnect portion comprising multiple metallization levels separated by an insulating region; and an antifuse structure coated with a portion of the insulating region, the antifuse structure comprising a beam held at two different points by two arms, a body, and an antifuse insulating zone, the beam, the body and the arms being metal and located within a same metallization level, the body and the beam mutually making contact via the antifuse insulating zone, the antifuse insulating zone configured to undergo breakdown in the presence of a breakdown potential difference between the body and the beam.

公开(公告)号：US10242944B2

公开(公告)日：2019-03-26

申请号：US15610323

申请日：2017-05-31

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara ,  Christian Rivero

IPC: H01L23/525 ,  H01L21/768 ,  H01L23/522

Abstract: An integrated circuit includes a substrate; an interconnect portion disposed over the substrate, the interconnect portion comprising multiple metallization levels separated by an insulating region; and an antifuse structure coated with a portion of the insulating region, the antifuse structure comprising a beam held at two different points by two arms, a body, and an antifuse insulating zone, the beam, the body and the arms being metal and located within a same metallization level, the body and the beam mutually making contact via the antifuse insulating zone, the antifuse insulating zone configured to undergo breakdown in the presence of a breakdown potential difference between the body and the beam.

公开(公告)号：US10229880B2

公开(公告)日：2019-03-12

申请号：US15379146

申请日：2016-12-14

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Jean-Philippe Escales

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/532 ,  H01L23/528 ,  H01L21/311 ,  H01L23/31

Abstract: A stack including a dual-passivation is etched locally so as to reveal contact pads of an integrated circuit which are situated above a last metallization level of an interconnection part of the integrated circuit. This stack serves to protect the integrated circuit against a breakdown of at least one dielectric region, at least in part porous, separating two electrically conducting elements of the interconnection part of the integrated circuit. Such a breakdown may occur due to electrical conduction assisted by the presence of defects within the at least one dielectric region.

公开(公告)号：US10211291B2

公开(公告)日：2019-02-19

申请号：US15864451

申请日：2018-01-08

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Guilhem Bouton ,  Pascal Fornara ,  Christian Rivero

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/06 ,  H01L21/762 ,  H01L21/763 ,  H01L27/112

Abstract: An integrated circuit includes a substrate and at least one component unfavorably sensitive to compressive stress which is arranged at least partially within an active region of the substrate limited by an insulating region. To address compressive stress in the active region, the circuit further includes at least one electrically inactive trench located at least in the insulating region and containing an internal area configured to reduce compressive stress in the active region. The internal area is filled with polysilicon. The polysilicon filled trench may further extend through the insulating region and into the substrate.

公开(公告)号：US10177101B2

公开(公告)日：2019-01-08

申请号：US15596767

申请日：2017-05-16

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Pascal Fornara ,  Guilhem Bouton ,  Mathieu Lisart

IPC: H01L23/00 ,  H01L21/311 ,  H01L23/528 ,  H01L27/088 ,  H01L23/522 ,  H01L23/58 ,  H01L21/768

Abstract: An integrated circuit includes a semiconductor substrate and a multitude of electrically conductive pads situated between component zones of the semiconductor substrate and a first metallization level of the integrated circuit, respectively. The multitude of electrically conductive pads are encapsulated in an insulating region and include: first pads, in electrical contact with corresponding first component zones, and at least one second pad, not in electrical contact with a corresponding second component zone.

公开(公告)号：US10026563B2

公开(公告)日：2018-07-17

申请号：US14289784

申请日：2014-05-29

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Antonio Di-Giacomo ,  Christian Rivero ,  Pascal Fornara

IPC: H01H1/00 ,  H01H61/00 ,  H01H37/00

Abstract: An integrated circuit, comprising an electrical-switching mechanical device in a housing having at least one first thermally deformable assembly including a beam held in at least two different locations by at least two arms secured to edges of the housing, the beam and the arms being metallic and situated within the same first metallization level and an electrically conductive body, wherein the said first thermally deformable assembly has at least one first configuration at a first temperature and a second configuration when at least one is at a second temperature different from the first temperature, wherein the beam is at a distance from the body in the first configuration and in contact with the said body and immobilized by the said body in the second configuration and establishing or prohibiting an electrical link passing through the body and through the beam.

公开(公告)号：US09916902B2

公开(公告)日：2018-03-13

申请号：US15218261

申请日：2016-07-25

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara ,  Christian Rivero

IPC: H01L23/00 ,  H01L27/115 ,  H01L21/82 ,  H01L29/78 ,  G11C16/22 ,  H01L21/311 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/74 ,  H01L21/66

CPC classification number: G11C16/22 ,  G06F21/87 ,  H01L21/31116 ,  H01L21/74 ,  H01L21/823481 ,  H01L21/823892 ,  H01L22/14 ,  H01L22/34 ,  H01L23/57 ,  H01L23/576 ,  H01L27/115 ,  H01L29/7846

Abstract: The thinning of a semiconductor substrate of an integrated circuit from a back face is detected using the measurement of a physical quantity representative of the resistance between the ends of two electrically-conducting contacts situated at an interface between an insulating region and an underlying substrate region. The two electrically-conducting contacts extend through the insulating region to reach the underlying substrate region.

公开(公告)号：US09754934B2

公开(公告)日：2017-09-05

申请号：US15383214

申请日：2016-12-19

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara ,  Christian Rivero

IPC: H01L23/52 ,  H01L27/06 ,  H01G5/011 ,  H01G5/16 ,  H01L23/528 ,  H01L23/522 ,  H01L49/02 ,  H01L21/768

CPC classification number: H01L27/0629 ,  H01G5/011 ,  H01G5/16 ,  H01L21/768 ,  H01L21/7682 ,  H01L21/7687 ,  H01L23/4821 ,  H01L23/5223 ,  H01L23/528 ,  H01L23/642 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/1461 ,  H01L2924/00

Abstract: A variable capacitor includes a fixed main capacitor electrode disposed in a first metal layer overlying a substrate, a second main capacitor electrode spaced from the fixed main capacitor electrode, and a movable capacitor electrode disposed in the first metal layer adjacent the fixed main capacitor electrode. The movable capacitor electrode can be caused to be in a first position ohmically electrically connected to the fixed main capacitor electrode such that the variable capacitor has a first capacitance value or in a second position spaced from the fixed main capacitor electrode such that the variable capacitor has a second capacitance value.