利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

111 条记录 (耗时 0.048 秒)

    Field programmable gate array with mask programmable I/O drivers
    81.
    发明授权
    Field programmable gate array with mask programmable I/O drivers 有权
    具有屏蔽可编程I / O驱动器的现场可编程门阵列

    公开(公告)号：US6091262A

    公开(公告)日：2000-07-18

    申请号：US236767

    申请日：1999-01-25

    申请人： Bernard J. New

    发明人： Bernard J. New

    IPC分类号： G06F7/38 ,  H03K19/177

    CPC分类号： H03K19/177 ,  H03K19/17704

    摘要： A field programmable gate array (FPGA) having a plurality of configurable logic blocks (CLBs). Each of the CLBs includes programmable interconnect resources, a field programmable configurable logic element (CLE) circuit and a corresponding non-field programmable gate array. The programmable interconnect resources are programmed to selectively couple or decouple each CLE circuit from its corresponding non-field programmable gate array. Dedicated interconnect resources enable adjacent non-field programmable gate arrays to be coupled. By coupling adjacent non-field programmable gate arrays, one or more relatively large non-field programmable gate arrays can be formed. The non-field programmable gate arrays have a greater logic density than the CLE circuits, thereby providing an improved logic density to the CLBs. Moreover, because each CLB includes a non-field programmable gate array, each of the CLE circuits is readily connectable to a non-field programmable gate array. The non-field programmable gate array can be used to provide a plurality of mask-programmable input/output driver circuits for connection to the pads of the FPGA.

    摘要翻译： 具有多个可配置逻辑块（CLB）的现场可编程门阵列（FPGA）。 每个CLB包括可编程互连资源，现场可编程可配置逻辑元件（CLE）电路和相应的非现场可编程门阵列。 可编程互连资源被编程为选择性地将每个CLE电路与其对应的非现场可编程门阵列耦合或去耦。 专用互连资源使相邻的非现场可编程门阵列耦合。 通过耦合相邻的非现场可编程门阵列，可以形成一个或多个相对大的非场可编程门阵列。 非现场可编程门阵列具有比CLE电路更大的逻辑密度，从而为CLB提供改进的逻辑密度。 而且，因为每个CLB都包括一个非现场可编程门阵列，所以每个CLE电路都可以很容易地连接到非现场可编程门阵列。 非现场可编程门阵列可用于提供用于连接到FPGA的焊盘的多个掩模可编程输入/输出驱动器电路。

    Partially reconfigurable FPGA and method of operating same
    82.
    发明授权
    Partially reconfigurable FPGA and method of operating same 失效
    部分可重新配置FPGA及其操作方法

    公开(公告)号：US6057704A

    公开(公告)日：2000-05-02

    申请号：US990154

    申请日：1997-12-12

    申请人： Bernard J. New ,  Charles R. Erickson

    发明人： Bernard J. New ,  Charles R. Erickson

    IPC分类号： H03K19/177 ,  G06F7/38 ,  G11C8/00 ,  G11C16/04

    CPC分类号： H03K19/17756 ,  H03K19/17704

    摘要： A field programmable gate array (FPGA) having an array of configuration memory cells arranged in rows and columns. The configuration memory cells store configuration data values for configuring the FPGA. Each configuration memory cell is coupled to a corresponding row line through a corresponding cell access transistor. A row access circuit is coupled to the row lines. To re-program a first set (but not a second set) of configuration memory cells in a column, the row access circuit initially pre-charges each of the row lines, and then provides configuration data values on a first set (but not a second set) of the row lines. All cell access transistors in the column are coupled to a column select line. To avoid losing data in any memory cell, a relatively low read voltage, followed by a higher write voltage, is applied to the column select line. When the read voltage is applied to the column select line, the associated cell access transistors are weakly turned on. As a result, the row lines are charged to states which correspond to the configuration data values stored by the configuration memory cells. Consequently, when the write voltage is subsequently applied to the column select line, configuration data values stored by the second set of configuration memory cells are not disturbed.

    摘要翻译： 具有排列成行和列的配置存储单元阵列的现场可编程门阵列（FPGA）。 配置存储单元存储用于配置FPGA的配置数据值。 每个配置存储单元通过相应的单元存取晶体管耦合到相应的行线。 行访问电路耦合到行线。 为了重新编程列中的配置存储器单元的第一组（但不是第二组），行访问电路首先预先对每行行进行预充电，然后在第一组（但不是第一组）上提供配置数据值 第二组）行行。 列中的所有单元存取晶体管耦合到列选择线。 为了避免在任何存储单元中丢失数据，将相对较低的读取电压（随后较高的写入电压）施加到列选择线。 当读取电压被施加到列选择线时，相关联的单元存取晶体管弱导通。 结果，行线被充电到对应于由配置存储器单元存储的配置数据值的状态。 因此，当写入电压随后被施加到列选择线时，由第二组配置存储单元存储的配置数据值不被干扰。

    Microprocessor with distributed registers accessible by programmable logic device
    83.
    发明授权
    Microprocessor with distributed registers accessible by programmable logic device 失效
    具有分布式寄存器的微处理器可由可编程逻辑器件访问

    公开(公告)号：US6026481A

    公开(公告)日：2000-02-15

    申请号：US964262

    申请日：1997-11-04

    申请人： Bernard J. New ,  William J. Harmon, Jr.

    发明人： Bernard J. New ,  William J. Harmon, Jr.

    IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F15/78 ,  H03K19/177 ,  G06F15/00

    CPC分类号： G06F9/3012 ,  G06F15/7867 ,  G06F9/3885 ,  G06F9/3897 ,  H03K19/177 ,  H03K19/17704

    摘要： A chip includes a programmable logic device and a microprocessor, wherein at least one of the associated registers of the microprocessor is distributed in the programmable logic device. The distributed register is coupled to both the microprocessor and the programmable logic device. In this manner, the microprocessor has the ability to access the register and place a value into the programmable logic device all in one clock cycle. Additionally, the logic functions in the programmable logic device are also advantageously available to the microprocessor.

    摘要翻译： 芯片包括可编程逻辑器件和微处理器，其中微处理器的相关寄存器中的至少一个分布在可编程逻辑器件中。 分布式寄存器耦合到微处理器和可编程逻辑器件。 以这种方式，微处理器能够在一个时钟周期内访问寄存器并将值置于可编程逻辑器件中。 此外，可编程逻辑器件中的逻辑功能也有利于微处理器。

    Field programmable gate array with dedicated computer bus interface and method for configuring both
    84.
    发明授权
    Field programmable gate array with dedicated computer bus interface and method for configuring both 失效
    具有专用计算机总线接口的现场可编程门阵列和两种配置方法

    公开(公告)号：US06011407A

    公开(公告)日：2000-01-04

    申请号：US876909

    申请日：1997-06-13

    申请人： Bernard J. New

    发明人： Bernard J. New

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17748 ,  H03K19/17732 ,  H03K19/17744

    摘要： A field programmable gate array is provided which has a programmable portion and a dedicated controller-interface circuit. The programmable portion includes conventional input/output (I/O) blocks and configurable logic blocks (CLBs). The controller-interface circuit allows the FPGA to be operably coupled to an external computer bus, such as a PCI bus. The programmable portion and the controller-interface circuit are separately programmable. As a result, after the controller-interface circuit is initialized, the programmable portion can be cleared and reconfigured without having to re-initialize the controller-interface circuit. The programmable portion is programmed in accordance with an implied addressing scheme in response to a configuration bit stream.

    摘要翻译： 提供了具有可编程部分和专用控制器接口电路的现场可编程门阵列。 可编程部分包括常规输入/输出（I / O）块和可配置逻辑块（CLB）。 控制器接口电路允许FPGA可操作地耦合到诸如PCI总线的外部计算机总线。 可编程部分和控制器接口电路可单独编程。 结果，在控制器接口电路被初始化之后，可以清除和重新配置可编程部分，而无需重新初始化控制器接口电路。 响应于配置位流，可编程部分根据隐含寻址方案进行编程。

    Composable memory array for a programmable logic device and method for implementing same
    85.
    发明授权
    Composable memory array for a programmable logic device and method for implementing same 失效
    可编程逻辑器件的可编程存储器阵列及其实现方法

    公开(公告)号：US5796269A

    公开(公告)日：1998-08-18

    申请号：US631298

    申请日：1996-04-09

    申请人： Bernard J. New

    发明人： Bernard J. New

    IPC分类号： H03K19/177 ,  H03K7/38

    CPC分类号： H03K19/1776

    摘要： A composable memory array for a programmable logic device includes a plurality of dedicated, serially coupled memory tiles. Each memory tile includes a plurality of dual-port memory cells, each having a first port and a second port, a plurality of first bit lines coupled to the first ports and a plurality of second data lines coupled to the second ports. The first and second bit lines extend across memory tiles. Each memory tile includes a plurality of first configuration circuits which allow the first bit lines of the memory tile to be coupled to the first bit lines of the previous memory tile. Thus, any number of consecutive memory tiles can be concatenated to form a memory array using the first set of bit lines. Non-consecutive memory tiles include a plurality of second configuration circuits which allow the second bit lines of the memory tile to be coupled to the second bit lines of a previous memory tile.

    摘要翻译： 用于可编程逻辑器件的可组合存储器阵列包括多个专用的串联存储器片。 每个存储器片包括多个双端口存储器单元，每个具有第一端口和第二端口，耦合到第一端口的多个第一位线和耦合到第二端口的多个第二数据线。 第一和第二位线跨越存储器块延伸。 每个存储器片包括多个第一配置电路，其允许存储器片的第一位线耦合到先前存储器片的第一位线。 因此，可以使用第一组位线来连接任何数量的连续存储器片，以形成存储器阵列。 非连续存储器片包括允许存储器片的第二位线耦合到先前存储器片的第二位线的多个第二配置电路。

    Structure and method for performing analog to digital conversion
    86.
    发明授权
    Structure and method for performing analog to digital conversion 失效
    用于执行模数转换的结构和方法

    公开(公告)号：US5502440A

    公开(公告)日：1996-03-26

    申请号：US300280

    申请日：1994-09-02

    申请人： Bernard J. New

    发明人： Bernard J. New

    IPC分类号： H03M1/56 ,  H03M1/60

    CPC分类号： H03M1/56

    摘要： A structure and method of performing an analog-to-digital conversion uses a voltage generator which generates an analog reference signal in response to a clock signal. The analog reference signal is a ramp signal which varies between two on-chip supply voltages. A voltage divider circuit receives an analog input signal to be digitized and the analog reference signal. The voltage divider circuit creates an analog control signal equal to the sum of a predetermined fraction of the analog input signal and a predetermined fraction of the analog reference signal. The analog control signal is provided to a first digital buffer and the analog reference signal is provided to a second digital buffer. The first and second digital buffers provide digital control signals having a first logic state when the applied input signal is less than a threshold voltage and having a second logic state when the applied input signal is greater than the threshold voltage. A digital logic circuit receives the digital control signals from the first and second digital buffers and the above-mentioned clock signal. In response, the digital logic circuit generates a digital output signal representative of the analog input signal.

    摘要翻译： 执行模数转换的结构和方法使用响应于时钟信号产生模拟参考信号的电压发生器。 模拟参考信号是在两个片上电源电压之间变化的斜坡信号。 分压电路接收要数字化的模拟输入信号和模拟参考信号。 分压器电路产生等于模拟输入信号的预定分数与模拟参考信号的预定分数之和的模拟控制信号。 将模拟控制信号提供给第一数字缓冲器，并将模拟参考信号提供给第二数字缓冲器。 当所施加的输入信号小于阈值电压时，第一和第二数字缓冲器提供具有第一逻辑状态的数字控制信号，并且当所施加的输入信号大于阈值电压时具有第二逻辑状态。 数字逻辑电路接收来自第一和第二数字缓冲器的数字控制信号和上述时钟信号。 作为响应，数字逻辑电路产生表示模拟输入信号的数字输出信号。

    Circuit for fast carry and logic
    87.
    发明授权
    Circuit for fast carry and logic 失效
    快速进位和逻辑电路

    公开(公告)号：US5481206A

    公开(公告)日：1996-01-02

    申请号：US310113

    申请日：1994-09-20

    申请人： Bernard J. New ,  Kerry M. Pierce

    发明人： Bernard J. New ,  Kerry M. Pierce

    IPC分类号： G06F7/38 ,  G06F7/00 ,  G06F7/50 ,  G06F7/503 ,  G06F7/506 ,  G06F7/507 ,  G06F7/57 ,  H03K19/173 ,  H03K19/177 ,  H03K19/20

    CPC分类号： G06F7/507 ,  G06F7/503 ,  H03K19/1737 ,  G06F2207/4812

    摘要： Programmable logic devices which include multiple blocks of combinatorial function generators and storage elements, and which are interconnected by a programmable interconnect structure are used, among other things for performing arithmetic functions which use logic for generating the carry function. When a large number of bits is to be processed, the carry function typically causes significant delay or requires significant additional components to achieve a result at high speed. The present invention provides dedicated hardware within the logic blocks for performing the carry function quickly and with a minimum number of components. The circuit includes additional structures to allow the fast carry hardware to perform additional commonly used functions.

    摘要翻译： 使用包括组合函数发生器和存储元件的多个块并且通过可编程互连结构互连的可编程逻辑器件，用于执行使用用于产生进位功能的逻辑的算术功能。 当要处理大量的位时，进位功能通常会导致显着的延迟或需要大量附加组件以高速获得结果。 本发明提供逻辑块内的专用硬件，用于快速执行进位功能并具有最少数量的部件。 该电路包括允许快速携带硬件执行附加常用功能的附加结构。