公开(公告)号：US06788584B2

公开(公告)日：2004-09-07

申请号：US10078106

申请日：2002-02-19

Applicant: Kerry D. Tedrow ,  Rajesh Sundaram

Inventor： Kerry D. Tedrow ,  Rajesh Sundaram

IPC: G11C700

CPC classification number: G11C16/12 ,  G11C16/08 ,  G11C16/16 ,  G11C16/30

Abstract: The present invention is in the field of flash memory. More particularly, embodiments of the present invention may provide a negative voltage for erasing when coupled to a memory cell to be erased and provide voltages to read or program when not coupled to a memory cell that is selected to be erased. Embodiments may also provide a high magnitude negative voltage to erase; a low impedance, low voltage current to read or program; and burn little to no current when not coupled to a memory cell that is selected to be erased.

Abstract translation: 本发明在闪速存储器领域。 更具体地说，本发明的实施例可以在耦合到待擦除的存储器单元时提供用于擦除的负电压，并且当未耦合到被选择要擦除的存储器单元时提供读取或编程的电压。 实施例还可以提供高幅度的负电压来擦除; 低阻抗，低电压电流读取或编程; 并且当不耦合到被选择被擦除的存储器单元时，几乎没有电流消耗。

公开(公告)号：US06628108B1

公开(公告)日：2003-09-30

申请号：US09746119

申请日：2000-12-22

Applicant: Mase Taub ,  Rajesh Sundaram ,  Kerry Tedrow

Inventor： Mase Taub ,  Rajesh Sundaram ,  Kerry Tedrow

IPC: G05F144

CPC classification number: G05F3/24 ,  G06F1/26

Abstract: A method and apparatus to provide a low voltage reference generation. The apparatus includes a reference voltage generator to receive a first input voltage signal and output a reference voltage signal. A voltage level detector electrically coupled to the reference voltage generator to receive the reference voltage signal and also receive a second input voltage signal. The voltage level detector compares the second input voltage signal to the reference voltage signal for generating an output based on the compared signals.

Abstract translation: 一种提供低电压参考电压的方法和装置。 该装置包括用于接收第一输入电压信号并输出​​参考电压信号的参考电压发生器。 电压电平检测器，电耦合到参考电压发生器以接收参考电压信号，并且还接收第二输入电压信号。 电压电平检测器将第二输入电压信号与参考电压信号进行比较，用于基于所比较的信号产生输出。

公开(公告)号：US06463004B2

公开(公告)日：2002-10-08

申请号：US09924922

申请日：2001-08-07

Applicant: Sandeep K. Guliani ,  Rajesh Sundaram ,  Mase J. Taub

Inventor： Sandeep K. Guliani ,  Rajesh Sundaram ,  Mase J. Taub

IPC: G11C800

CPC classification number: G11C16/30 ,  G11C5/14 ,  G11C8/12

Abstract: A method for a VPX banked architecture. The method of one embodiment first segments a memory array into at least two banks. Each bank including memory cells. The banks are provided with a supply voltage.

公开(公告)号：US06449211B1

公开(公告)日：2002-09-10

申请号：US09945021

申请日：2001-08-31

Applicant: Owen W. Jungroth ,  Rajesh Sundaram ,  Mase J. Taub ,  Rupinder K. Bains ,  Raymond Zeng ,  Binh N. Ngo ,  Bharat Pathak

Inventor： Owen W. Jungroth ,  Rajesh Sundaram ,  Mase J. Taub ,  Rupinder K. Bains ,  Raymond Zeng ,  Binh N. Ngo ,  Bharat Pathak

IPC: G11C800

CPC classification number: G11C16/30 ,  G11C5/147 ,  G11C8/08

Abstract: A circuit includes (i) an N-channel device having a gate, a source connected to low voltage, and a drain connected to a memory select gate, (ii) a P-channel device having a gate, a source, and a drain connected to the drain of the N-channel device, and (iii) a voltage supply connected to the source of the P-channel device, the voltage supply switching between a first high voltage and a first lower voltage. A gate driver supplies, to the gates of the N-channel and P-channel devices, a second high voltage, a second low voltage, or an intermediary voltage between the second high voltage and second low voltage. The gate driver supplies the intermediary voltage when the voltage supply switches between the first high voltage and first lower voltage.

Abstract translation: 电路包括（i）具有栅极，连接到低电压的源极和连接到存储器选择栅极的漏极的N沟道器件，（ii）具有栅极，源极和漏极的P沟道器件 连接到N沟道器件的漏极，以及（iii）连接到P沟道器件源极的电压源，电压源在第一高电压和第一较低电压之间切换。 栅极驱动器向N沟道和P沟道器件的栅极提供第二高电压，第二低电压或第二高电压和第二低电压之间的中间电压。 当电源在第一高电压和第一低电压之间切换时，栅极驱动器提供中间电压。

公开(公告)号：US06434073B1

公开(公告)日：2002-08-13

申请号：US09924888

申请日：2001-08-07

Applicant: Sandeep K. Guliani ,  Rajesh Sundaram ,  Mase J. Taub

Inventor： Sandeep K. Guliani ,  Rajesh Sundaram ,  Mase J. Taub

IPC: G11C702

Abstract: A method for a VPX banked architecture. The method of one embodiment first segments a memory array into at least two banks. Each bank including memory cells. The banks are provided with a supply voltage.

公开(公告)号：US06359814B1

公开(公告)日：2002-03-19

申请号：US09753351

申请日：2000-12-29

Applicant: Rajesh Sundaram ,  Kerry D. Tedrow

Inventor： Rajesh Sundaram ,  Kerry D. Tedrow

IPC: G11C700

CPC classification number: H02M3/07 ,  G11C11/22 ,  H02M2003/071

Abstract: A negative voltage charge pump including a regulation circuit. The regulation circuit has a level shift ladder including a plurality of level shifters connected in series. One end of the level shift ladder receives a power supply voltage and the other end receives the negative output of the charge pump. A feedback voltage is generated from one of the intermediate nodes of the level shift ladder. A differential amplifier generates a regulation voltage which varies as a function of the feedback voltage and a reference voltage. The regulation voltage is applied to a frequency control input of a voltage-controlled oscillator for generating a signal that drives the charge pump. Each of the level shifters of the level shift ladder can be a triple well device that can be configured to handle negative voltages without forward biasing an internal p-n junction.

Abstract translation: 负电压电荷泵，包括调节电路。 调节电路具有包括串联连接的多个电平移位器的电平移位梯形图。 电平转换梯的一端接收电源电压，另一端接收电荷泵的负输出。 从电平转换梯的中间节点之一产生反馈电压。 差分放大器产生作为反馈电压和参考电压的函数而变化的调节电压。 调节电压被施加到压控振荡器的频率控制输入端，用于产生驱动电荷泵的信号。 电平变换梯级的每个电平移位器可以是三阱器件，其可被配置为处理负电压而不向前偏置内部p-n结。