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公开(公告)号：US06463004B2
公开(公告)日：2002-10-08
申请号：US09924922
申请日：2001-08-07
IPC分类号： G11C800
摘要： A method for a VPX banked architecture. The method of one embodiment first segments a memory array into at least two banks. Each bank including memory cells. The banks are provided with a supply voltage.
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公开(公告)号：US06434073B1
公开(公告)日：2002-08-13
申请号：US09924888
申请日：2001-08-07
IPC分类号： G11C702
摘要： A method for a VPX banked architecture. The method of one embodiment first segments a memory array into at least two banks. Each bank including memory cells. The banks are provided with a supply voltage.
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公开(公告)号：US06459645B2
公开(公告)日：2002-10-01
申请号：US09410493
申请日：1999-09-30
IPC分类号： G11C800
摘要： A method and apparatus to segment a programmable non-volatile memory array into at least two banks. The banks include memory cells. Each bank in the at least two banks is provided with a local programming voltage. Each local programming voltage is independent of the other local programming voltages supplied to the other banks.
摘要翻译： 一种将可编程非易失性存储器阵列分割成至少两个存储体的方法和装置。 银行包括存储单元。 至少两个组中的每个存储体都具有本地编程电压。 每个本地编程电压与提供给其他存储体的其他本地编程电压无关。
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公开(公告)号：US20150348627A1
公开(公告)日：2015-12-03
申请号：US14289858
申请日：2014-05-29
申请人： Mase J Taub , Sandeep K. Guliani , Kiran Pangal
发明人： Mase J Taub , Sandeep K. Guliani , Kiran Pangal
IPC分类号： G11C13/00
CPC分类号： G11C13/0004 , G11C5/02 , G11C7/00 , G11C13/004 , G11C13/0069 , G11C2013/0076 , G11C2013/0078 , G11C2013/0092 , G11C2213/77
摘要： A system and technique is disclosed for writing data in a cross-point memory. The state of one or more memory cells of the cross-point memory are sensed and then are continued to be selected and left on. It is then determined which of the one or more memory cells are to change state based on incoming user data that is to be written into the one or more memory cells. The one or more memory cells determined to change state and are still selected to be on are then written by applying a write-current pulse to the memory cells. In one exemplary embodiment, the one or more memory cells comprise one or more phase-change-type memory cell devices.
摘要翻译： 公开了用于在交叉点存储器中写入数据的系统和技术。 检测交叉点存储器的一个或多个存储单元的状态，然后继续选择并保持。 然后，基于要写入一个或多个存储器单元的输入用户数据，确定一个或多个存储器单元中的哪一个将改变状态。 然后通过向存储器单元施加写入电流脉冲来写入确定为改变状态并且仍被选择为导通的一个或多个存储器单元。 在一个示例性实施例中，一个或多个存储器单元包括一个或多个相变型存储单元器件。
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公开(公告)号：US06629047B1
公开(公告)日：2003-09-30
申请号：US09539475
申请日：2000-03-30
IPC分类号： G11C1300
CPC分类号： G11C5/147 , G11C16/225
摘要： A method for voltage detection and lockout. The method of one embodiment first compares a reference voltage to a supply voltage to determine whether the voltage supply voltage is greater than the reference voltage. The reference voltage is validated by determining whether the reference voltage is at least a valid voltage potential. An unlock signal is generated if the supply voltage is greater than the reference voltage and if the reference voltage is valid.
摘要翻译： 一种电压检测和锁定的方法。 一个实施例的方法首先将参考电压与电源电压进行比较，以确定电压电源电压是否大于参考电压。 参考电压通过确定参考电压是否至少是有效的电压电位来验证。 如果电源电压大于参考电压，并且参考电压有效，则产生解锁信号。
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公开(公告)号：US06789027B2
公开(公告)日：2004-09-07
申请号：US10436745
申请日：2003-05-12
IPC分类号： G11C1300
CPC分类号： G11C5/147 , G11C16/225
摘要： A method for voltage detection and lockout. The method of one embodiment first compares a reference voltage to a supply voltage to determine whether the voltage supply voltage is greater than the reference voltage. The reference voltage is validated by determining whether the reference voltage is at least a valid voltage potential. An unlock signal is generated if the supply voltage is greater than the reference voltage and if the reference voltage is valid.
摘要翻译： 一种电压检测和锁定的方法。 一个实施例的方法首先将参考电压与电源电压进行比较，以确定电压电源电压是否大于参考电压。 参考电压通过确定参考电压是否至少是有效的电压电位来验证。 如果电源电压大于参考电压，并且参考电压有效，则产生解锁信号。
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7.发明授权Method and apparatus for achieving low standby power using a positive temperature correlated clock frequency 失效使用正温度相关时钟频率实现低待机功率的方法和装置
公开(公告)号：US6163225A
公开(公告)日：2000-12-19
申请号：US305976
申请日：1999-05-05
摘要： A method for generating a positive temperature correlated clock frequency is described. The method comprises conducting current through a resistor to charge a capacitor. When the capacitor is charged to a trip point of the inverter at the input of the inverter chain, a transition in an output signal of an inverter chain is triggered. The capacitor is discharged through a grounding device when the output signal activates said grounding device.
摘要翻译： 描述了用于产生正温度相关时钟频率的方法。 该方法包括通过电阻器传导电流以对电容器充电。 当电抗器在变频器链的输入端被充电到变频器的跳变点时，触发逆变器链输出信号的转变。 当输出信号激活所述接地装置时，电容器通过接地装置放电。
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8.发明授权Method and apparatus for fast production programming and low-voltage in-system writes for programmable logic device 失效用于可编程逻辑器件的快速生产编程和低压系统写入的方法和装置
公开(公告)号：US6150835A
公开(公告)日：2000-11-21
申请号：US75430
申请日：1998-05-08
IPC分类号： G11C7/00 , G05F1/10 , G05F3/02 , H03K19/173 , H03K19/177 , H01L25/00 , H03K5/22
CPC分类号： H03K19/17748 , H03K19/1778
摘要： A programmable logic device that includes a voltage input and a detection circuit coupled to the voltage input is described. The detection circuit detects whether a voltage applied to the voltage input exceeds a predetermined value. The programmable logic device also includes a configuration circuit coupled to the detection circuit. The configuration circuit configures the programmable logic device to receive a current sufficient for program and erase operations through the voltage input in response to the detection circuit detecting that the voltage exceeds the predetermined value.
摘要翻译： 描述了包括电压输入和耦合到电压输入的检测电路的可编程逻辑器件。 检测电路检测施加到电压输入的电压是否超过预定值。 可编程逻辑器件还包括耦合到检测电路的配置电路。 配置电路配置可编程逻辑器件，以响应于检测电路检测到电压超过预定值，通过电压输入接收足以进行编程和擦除操作的电流。
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公开(公告)号：US5109187A
公开(公告)日：1992-04-28
申请号：US589698
申请日：1990-09-28
申请人： Sandeep K. Guliani
发明人： Sandeep K. Guliani
摘要： A circuit is described as a generating supply-independent voltage reference. In MOS technology, a current mirror section incorporating a pair of N-channel and W-channel tracking devices are coupled to a power supply V.sub.cc for generating a voltage reference output that is directly proportional to V.sub.tn -V.sub.tw. V.sub.tn is the gate threshold voltage of the N-channel device, while V.sub.tw is the gate threshold voltage of W-channel device. A start-up circuit is further coupled to the power supply V.sub.cc and to the current mirror section for maintaining the operating point V.sub.1 of the circuit that is independent of supply voltage. The degree of supply independence can be further increased by adding a pair of P-channel device to the output of the present invention. Thus, the present invention generates a voltage reference that is independent from power supply, temperature and process while minimizing power dissipation. When the present invention replaces the power supply to the sensing circuit of non-volatile memory devices such as an EPROM the overshoot encountered during the read mode is minimized. It follows that the present invention not only solves one of the key yield losses seen on non-volatile memory devices but also improves the access time for the same devices.
摘要翻译： 电路被描述为产生电源独立电压基准。 在MOS技术中，结合有一对N沟道和W沟道跟踪器件的电流镜部分耦合到电源Vcc，用于产生与Vtn-Vtw成正比的电压基准输出。 Vtn是N沟道器件的栅极阈值电压，而Vtw是W沟道器件的栅极阈值电压。 启动电路还耦合到电源Vcc和电流镜部分，用于维持电路的工作点V1，其独立于电源电压。 通过向本发明的输出添加一对P沟道器件，可以进一步提高供给的独立性。 因此，本发明在功率耗散最小化的同时产生独立于电源，温度和过程的电压基准。 当本发明替代诸如EPROM的非易失性存储器件的感测电路的电源时，读取模式期间遇到的过冲被最小化。 因此，本发明不仅解决了在非易失性存储器件上看到的关键产量损失之一，而且改善了相同器件的访问时间。
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公开(公告)号：US5373508A
公开(公告)日：1994-12-13
申请号：US923853
申请日：1992-07-31
申请人： Sandeep K. Guliani
发明人： Sandeep K. Guliani
CPC分类号： H04L25/062
摘要： Two parallel valid data detectors are provided to detect whether a sinusoidal electrical signal from a twisted pair medium represents valid data. One handles phase 0 degree starting sinusoidal electrical signal, the other handle phase 180 degree. In either case, the valid data detectors receive two series of pulses as input, indicating positive and negative differences respectively between RD and RD from the twisted pair medium. In response, if the valid data detector detects the proper data pattern within a predetermined time frame, it outputs a signal indicating the detection of valid data. The "phase 0" valid data detector looks for a high to low and back to high data pattern, whereas, the "phase 180" valid data detector looks for a low to high and back to low data pattern. Additionally, a signal magnitude detector is provided to detect magnitude differences between RD+ and RD- from the twisted pair medium, and generate the positive and a negative series of pulses for the valid data detectors, as long as the magnitude differences exceeded a predetermined minimum threshold. Furthermore, a signal synchronizer is provided to receive the valid data detection signal from either valid data detector, and synchronize the generated signal to the internal clock of the receiving circuit.
摘要翻译： 提供两个并行的有效数据检测器来检测来自双绞线介质的正弦电信号是否表示有效数据。 一个处理相位0度起始正弦电信号，另一个手柄相位180度。 在任一种情况下，有效的数据检测器都接收两个串联的脉冲作为输入，分别表示来自双绞线介质的RD和RD之间的正负差异。 作为响应，如果有效数据检测器在预定时间帧内检测到适当的数据模式，则输出指示检测有效数据的信号。 “0”有效数据检测器寻找高到低的数据模式，而“相180”有效的数据检测器寻找低到高和回到低的数据模式。 此外，提供信号幅度检测器以检测来自双绞线介质的RD +和RD-之间的幅度差异，并产生用于有效数据检测器的正序列和负序脉冲，只要幅度差超过预定的最小阈值 。 此外，提供信号同步器以从有效数据检测器接收有效数据检测信号，并将所生成的信号同步到接收电路的内部时钟。
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