公开(公告)号：US06944065B2

公开(公告)日：2005-09-13

申请号：US10877634

申请日：2004-06-25

Applicant: Kerry D. Tedrow ,  Rajesh Sundaram

Inventor： Kerry D. Tedrow ,  Rajesh Sundaram

IPC: G11C16/08 ,  G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C7/00

CPC classification number: G11C16/12 ,  G11C16/08 ,  G11C16/16 ,  G11C16/30

Abstract: The present invention is in the field of flash memory. More particularly, embodiments of the present invention may provide a negative voltage for erasing when coupled to a memory cell to be erased and provide voltages to read or program when not coupled to a memory cell that is selected to be erased. Embodiments may also provide a high magnitude negative voltage to erase; a low impedance, low voltage current to read or program; and burn little to no current when not coupled to a memory cell that is selected to be erased.

Abstract translation: 本发明在闪速存储器领域。 更具体地说，本发明的实施例可以在耦合到待擦除的存储器单元时提供用于擦除的负电压，并且当未耦合到被选择要擦除的存储器单元时提供读取或编程的电压。 实施例还可以提供高幅度的负电压来擦除; 低阻抗，低电压电流读取或编程; 并且当不耦合到被选择被擦除的存储器单元时，几乎没有电流消耗。

公开(公告)号：US06477091B2

公开(公告)日：2002-11-05

申请号：US09823463

申请日：2001-03-30

Applicant: Kerry D. Tedrow ,  Rajesh Sundaram

Inventor： Kerry D. Tedrow ,  Rajesh Sundaram

IPC: G11C700

CPC classification number: G11C16/12 ,  G11C16/08 ,  G11C16/16 ,  G11C16/30

Abstract: The present invention is in the field of flash memory. More particularly, embodiments of the present invention may provide a negative voltage for erasing when coupled to a memory cell to be erased and provide voltages to read or program when not coupled to a memory cell that is selected to be erased. Embodiments may also provide a high magnitude negative voltage to erase; a low impedance, low voltage current to read or program; and burn little to no current when not coupled to a memory cell that is selected to be erased.

Abstract translation: 本发明在闪速存储器领域。 更具体地说，本发明的实施例可以在耦合到待擦除的存储器单元时提供用于擦除的负电压，并且当未耦合到被选择要擦除的存储器单元时提供读取或编程的电压。 实施例还可以提供高幅度的负电压来擦除; 低阻抗，低电压电流读取或编程; 并且当不耦合到被选择被擦除的存储器单元时，几乎没有电流消耗。

公开(公告)号：US07319616B2

公开(公告)日：2008-01-15

申请号：US10713841

申请日：2003-11-13

Applicant: Rajesh Sundaram ,  Jahanshir Javanifard ,  Kerry D. Tedrow ,  Priya Walimbe ,  Tom H. Ly ,  Raymond W. Zeng

Inventor： Rajesh Sundaram ,  Jahanshir Javanifard ,  Kerry D. Tedrow ,  Priya Walimbe ,  Tom H. Ly ,  Raymond W. Zeng

IPC: G11C16/06

CPC classification number: G11C16/08 ,  G11C8/08

Abstract: In one embodiment, the present invention includes a method to supply a negative voltage to at least one deselected wordline of a memory array. Further, while the negative voltage is supplied to deselected wordlines, a positive voltage may be supplied to a selected wordline. The memory array may be a flash memory incorporating multi-level cell architecture, in one embodiment.

Abstract translation: 在一个实施例中，本发明包括将负电压提供给存储器阵列的至少一个未选择的字线的方法。 此外，当将负电压提供给未选择的字线时，可以向所选择的字线提供正电压。 在一个实施例中，存储器阵列可以是并入多级单元架构的闪速存储器。

公开(公告)号：US06788584B2

公开(公告)日：2004-09-07

申请号：US10078106

申请日：2002-02-19

Applicant: Kerry D. Tedrow ,  Rajesh Sundaram

Inventor： Kerry D. Tedrow ,  Rajesh Sundaram

IPC: G11C700

CPC classification number: G11C16/12 ,  G11C16/08 ,  G11C16/16 ,  G11C16/30

Abstract: The present invention is in the field of flash memory. More particularly, embodiments of the present invention may provide a negative voltage for erasing when coupled to a memory cell to be erased and provide voltages to read or program when not coupled to a memory cell that is selected to be erased. Embodiments may also provide a high magnitude negative voltage to erase; a low impedance, low voltage current to read or program; and burn little to no current when not coupled to a memory cell that is selected to be erased.

Abstract translation: 本发明在闪速存储器领域。 更具体地说，本发明的实施例可以在耦合到待擦除的存储器单元时提供用于擦除的负电压，并且当未耦合到被选择要擦除的存储器单元时提供读取或编程的电压。 实施例还可以提供高幅度的负电压来擦除; 低阻抗，低电压电流读取或编程; 并且当不耦合到被选择被擦除的存储器单元时，几乎没有电流消耗。

公开(公告)号：US06359814B1

公开(公告)日：2002-03-19

申请号：US09753351

申请日：2000-12-29

Applicant: Rajesh Sundaram ,  Kerry D. Tedrow

Inventor： Rajesh Sundaram ,  Kerry D. Tedrow

IPC: G11C700

CPC classification number: H02M3/07 ,  G11C11/22 ,  H02M2003/071

Abstract: A negative voltage charge pump including a regulation circuit. The regulation circuit has a level shift ladder including a plurality of level shifters connected in series. One end of the level shift ladder receives a power supply voltage and the other end receives the negative output of the charge pump. A feedback voltage is generated from one of the intermediate nodes of the level shift ladder. A differential amplifier generates a regulation voltage which varies as a function of the feedback voltage and a reference voltage. The regulation voltage is applied to a frequency control input of a voltage-controlled oscillator for generating a signal that drives the charge pump. Each of the level shifters of the level shift ladder can be a triple well device that can be configured to handle negative voltages without forward biasing an internal p-n junction.

Abstract translation: 负电压电荷泵，包括调节电路。 调节电路具有包括串联连接的多个电平移位器的电平移位梯形图。 电平转换梯的一端接收电源电压，另一端接收电荷泵的负输出。 从电平转换梯的中间节点之一产生反馈电压。 差分放大器产生作为反馈电压和参考电压的函数而变化的调节电压。 调节电压被施加到压控振荡器的频率控制输入端，用于产生驱动电荷泵的信号。 电平变换梯级的每个电平移位器可以是三阱器件，其可被配置为处理负电压而不向前偏置内部p-n结。

公开(公告)号：US09274885B2

公开(公告)日：2016-03-01

申请号：US13997246

申请日：2011-12-30

Applicant: Shekoufeh Qawami ,  Rajesh Sundaram

Inventor： Shekoufeh Qawami ,  Rajesh Sundaram

IPC: G11C29/00 ,  G06F11/10 ,  G06F11/07 ,  G11C13/00

CPC classification number: G06F11/1048 ,  G06F11/073 ,  G06F11/0763 ,  G06F11/1068 ,  G11C13/0004

Abstract: Methods and apparatus related to PCMS (Phase Change Memory with Switch) write error detection are described. In one embodiment, a first storage unit stores a single bit to indicate whether an error corresponding to a write operation in any of one or more PCMS devices has occurred. Also, one or more storage units each store a plurality of bits to indicate whether the error corresponding to the write operation has occurred in a partition of a plurality of partitions of the one or more PCMS devices. Other embodiments are also disclosed and claimed.

Abstract translation: 描述了与PCMS（带切换的相变存储器）写入错误检测相关的方法和装置。 在一个实施例中，第一存储单元存储单个位以指示是否发生了与一个或多个PCMS设备中的任一个中的写入操作相对应的错误。 此外，一个或多个存储单元每个存储多个位以指示与一个或多个PCMS设备的多个分区的分区中是否发生了与写入操作相对应的错误。 还公开并要求保护其他实施例。

公开(公告)号：US20130238832A1

公开(公告)日：2013-09-12

申请号：US13413898

申请日：2012-03-07

Applicant: Ravikanth Dronamraju ,  Douglas P. Doucette ,  Rajesh Sundaram

Inventor： Ravikanth Dronamraju ,  Douglas P. Doucette ,  Rajesh Sundaram

IPC: G06F12/00 ,  G06F12/08

CPC classification number: G06F3/0641 ,  G06F3/0608 ,  G06F3/0685 ,  G06F12/0866 ,  G06F2212/217 ,  G06F2212/461

Abstract: Methods and apparatuses for performing deduplication in a hybrid storage aggregate are provided. In one example, a method includes operating a hybrid storage aggregate that includes a plurality of tiers of different types of physical storage media. The method includes identifying a first storage block and a second storage block of the hybrid storage aggregate that contain identical data and identifying caching statuses of the first storage block and the second storage block. The method also includes deduplicating the first storage block and the second storage block based on the caching statuses of the first storage block and the second storage block.

Abstract translation: 提供了用于在混合存储集合中执行重复数据消除的方法和装置。 在一个示例中，方法包括操作包括多个不同类型的物理存储介质的混合存储集合。 该方法包括识别包含相同数据并识别第一存储块和第二存储块的高速缓存状态的混合存储聚合的第一存储块和第二存储块。 该方法还包括基于第一存储块和第二存储块的高速缓存状态对第一存储块和第二存储块进行重复数据删除。

公开(公告)号：US07979633B2

公开(公告)日：2011-07-12

申请号：US10817212

申请日：2004-04-02

Applicant: Steven R. Kleiman ,  Rajesh Sundaram ,  Douglas P. Doucette ,  Stephen H. Strange ,  Srinivasan Viswanathan

Inventor： Steven R. Kleiman ,  Rajesh Sundaram ,  Douglas P. Doucette ,  Stephen H. Strange ,  Srinivasan Viswanathan

IPC: G06F12/16

CPC classification number: G06F3/0613 ,  G06F3/0643 ,  G06F3/0655 ,  G06F3/0689 ,  G06F11/1076

Abstract: The invention features a method for controlling storage of data in a plurality of storage devices each including storage blocks, for example, in a RAID array. The method includes receiving a plurality of write requests associated with data, and buffering the write requests. A file system defines a group of storage blocks, responsive to disk topology information. The group includes a plurality of storage blocks in each of the plurality of storage devices. Each data block of the data to be written is associated with a respective one of the storage blocks, for transmitting the association to the plurality of storage devices.

Abstract translation: 本发明的特征在于一种用于控制多个存储设备中的数据存储的方法，每个存储设备包括例如RAID阵列中的存储块。 该方法包括接收与数据相关联的多个写入请求，并缓冲写入请求。 文件系统根据磁盘拓扑信息定义一组存储块。 该组包括多个存储装置中的每一个中的多个存储块。 要写入的数据的每个数据块与相应的一个存储块相关联，用于将关联发送到多个存储设备。

公开(公告)号：US07945822B1

公开(公告)日：2011-05-17

申请号：US12430783

申请日：2009-04-27

Applicant: Jeffrey S. Kimmel ,  Rajesh Sundaram ,  George Totolos, Jr. ,  Michael W. J. Hordijk

Inventor： Jeffrey S. Kimmel ,  Rajesh Sundaram ,  George Totolos, Jr. ,  Michael W. J. Hordijk

IPC: G11C29/00

CPC classification number: G06F12/0246 ,  G06F11/1666 ,  G06F11/20 ,  G06F2212/1032 ,  G06F2212/7208 ,  G11C29/76

Abstract: Described herein are method and apparatus for storing data to a low-latency random read memory (LLRRM) device using non-aligned data striping, the LLRRM device being implemented on a storage system. The LLRRM device may comprise a bank comprising a plurality of memory chips, each chip being simultaneously accessible for storing data on a plurality of erase-units (EUs). A storage operating system may maintain, for each chip, a reserve data structure listing reserve EUs and a remapping data structure for tracking remappings between defective EUs to reserve EUs in the chip. A defective EU in a chip may be mapped to a reserve EU from the reserve data structure. Upon receiving a data block to be stored to the LLRRM device at the defective EU, the storage operating system may stripe the received data block across a plurality of chips in a non-aligned manner using the remapped reserve EU.

Abstract translation: 这里描述了使用非对齐数据条带化将数据存储到低延迟随机读取存储器（LLRRM）装置的方法和装置，LLRRM装置在存储系统上实现。 LLRRM设备可以包括一个包括多个存储器芯片的存储体，每个芯片可以同时访问以存储多个擦除单元（EU）上的数据。 存储操作系统可以为每个芯片保留列出保留EU的备用数据结构和用于跟踪缺陷EU之间的重新映射的重映射数据结构，以在芯片中保留EU。 芯片中的有缺陷的EU可以从保留数据结构映射到保留EU。 在接收到在缺陷EU处存储到LLRRM设备的数据块时，存储操作系统可以使用重新映射的保留EU以不对齐的方式跨越多个芯片对接收到的数据块进行条带化。

公开(公告)号：US07685462B1

公开(公告)日：2010-03-23

申请号：US11970784

申请日：2008-01-08

Applicant: James Leong ,  Scott Schoenthal ,  Srinivasan Viswanathan ,  Rajesh Sundaram

Inventor： James Leong ,  Scott Schoenthal ,  Srinivasan Viswanathan ,  Rajesh Sundaram

IPC: G06F11/00

CPC classification number: G06F11/2087

Abstract: A method for operating a data storage system is described. The method first constructs an I/O tree representing a logical configuration of storage devices coupled to the storage system, the I/O tree representing a flow of I/O operations to the storage devices. Elements of the I/O tree are represented by objects. A freeze condition is imposed on a selected object of the I/O tree in order to disable a portion of the storage devices serviced by the selected object. Configuration management operations are performed on the portion of the storage devices serviced by the selected object. The freeze condition is removed from the selected object in response to completion of the configuration management, in order to resume I/O operations to the portion of the storage devices serviced by the selected object.

Abstract translation: 描述了一种用于操作数据存储系统的方法。 该方法首先构建表示耦合到存储系统的存储设备的逻辑配置的I / O树，该I / O树表示到存储设备的I / O操作流。 I / O树的元素由对象表示。 对I / O树的所选对象施加冻结条件，以便禁用所选对象所服务的存储设备的一部分。 对所选对象所服务的存储设备的部分执行配置管理操作。 响应于配置管理的完成，从所选对象中删除冻结条件，以便恢复对所选对象所服务的存储设备的部分的I / O操作。