公开(公告)号：US11637069B2

公开(公告)日：2023-04-25

申请号：US17220345

申请日：2021-04-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jung-Chan Yang ,  Chi-Yu Lu ,  Hui-Zhong Zhuang ,  Chih-Liang Chen

IPC: H01L23/535 ,  H01L21/768 ,  H01L29/40 ,  H01L29/417 ,  H01L23/522 ,  H01L21/8234 ,  H01L23/538 ,  H01L27/02 ,  H01L23/528

Abstract: A semiconductor device including: an active region; first, second and third metal-to-drain/source (MD) contact structures which extend in a first direction and correspondingly overlap the active region; a via-to-via (V2V) rail which extends in a second direction perpendicular to the first direction, and overlaps the first, second and third MD contact structures; a first conductive segment which overlaps the V2V rail, is in a first metallization layer, and, relative to the second direction, overlaps each of the first, second and third MD contact structures; and a first via-to-MD (VD) structure between the first MD contact structure and the first conductive segment, the first VD structure electrically coupling the first conductive segment, the V2V rail and the first MD contact structure; wherein at least one of the second or third MD contact structures is electrically decoupled from the V2V rail.

公开(公告)号：US11362110B2

公开(公告)日：2022-06-14

申请号：US16927740

申请日：2020-07-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Pochun Wang ,  Guo-Huei Wu ,  Hui-Zhong Zhuang ,  Chih-Liang Chen ,  Li-Chun Tien

IPC: H01L27/12 ,  H01L21/84 ,  H01L23/522 ,  H01L23/528 ,  H01L21/74 ,  H01L21/768 ,  H01L21/822 ,  H01L21/423 ,  H01L29/786 ,  H01L27/06

Abstract: A semiconductor structure includes a first transistor, a second transistor, a first dummy source/drain, a third transistor, a fourth transistor, and a second dummy source/drain. The first transistor and a second transistor adjacent to the first transistor are at a first elevation. The first dummy source/drain is disposed at the first elevation. The third transistor and a fourth transistor adjacent to the third transistor, are at a second elevation different from the first elevation. The second dummy source/drain is disposed at the second elevation. The second transistor is vertically aligned with the third transistor. The first dummy source/drain is vertically aligned with a source/drain of the fourth transistor. The second dummy source/drain is vertically aligned with a source/drain of the first transistor. The gate structure between the second dummy source/drain and a source/drain of the third transistor is absent. A method for manufacturing a semiconductor structure is also provided.

公开(公告)号：US11296682B2

公开(公告)日：2022-04-05

申请号：US16837886

申请日：2020-04-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Jin-Wei Xu ,  Hui-Zhong Zhuang ,  Chih-Liang Chen

IPC: H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H03K3/356

Abstract: An input circuit of a flip-flop includes: a first gate strip, a second gate strip and a third gate strip. The first gate strip is a co-gate terminal of a first PMOS and a first NMOS; the second gate strip is disposed immediately adjacent to the first gate strip, and a co-gate terminal of a second PMOS and a second NMOS. The first PMOS and the second PMOS share a doping region as a co-source terminal. The first NMOS and the second NMOS share a doping region as a co-source terminal. The third gate strip is disposed immediately adjacent to the second gate strip. The third gate strip is a co-gate terminal of a third PMOS and a third NMOS. The second PMOS and the third PMOS share a doping region as a co-drain terminal. The second NMOS and the third NMOS share a doping region as a co-drain terminal.

公开(公告)号：US11188703B2

公开(公告)日：2021-11-30

申请号：US16579138

申请日：2019-09-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Sang-Chi Huang ,  Hui-Zhong Zhuang ,  Jung-Chan Yang ,  Pochun Wang

IPC: G06F30/394 ,  H01L27/02 ,  G06F30/392

Abstract: A method of forming an integrated circuit includes generating a first and a second standard cell layout design, generating a first set of cut feature layout patterns extending in a first direction, and manufacturing the integrated circuit based on the first or second standard cell layout design. Generating the first standard cell layout design includes generating a first set of conductive feature layout patterns extending in the first direction, and overlapping a first set of gridlines extending in the first direction. Generating the second standard cell layout design includes generating a second set of conductive feature layout patterns extending in the first direction and overlapping a second set of gridlines extending in the first direction. A side of a first cut feature layout pattern extending in the first direction is aligned with a first gridline of the first or second set of gridlines.

公开(公告)号：US11100273B2

公开(公告)日：2021-08-24

申请号：US16674869

申请日：2019-11-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shih-Wei Peng ,  Chih-Liang Chen ,  Charles Chew-Yuen Young ,  Hui-Zhong Zhuang ,  Jiann-Tyng Tzeng ,  Shun Li Chen ,  Wei-Cheng Lin

IPC: G06F30/00 ,  G06F30/398 ,  H01L27/02 ,  H01L27/118 ,  G06F30/39 ,  G06F30/394

Abstract: A method of forming an integrated circuit includes generating, by a processor, a layout design of the integrated circuit based on a set of design rules and manufacturing the integrated circuit based on the layout design. The generating of the layout design includes generating a set of active region layout patterns extending in a first direction, generating a set of gate layout patterns extending in a second direction, and generating a cut feature layout pattern extending in the first direction, overlapping at least a first gate layout pattern of the set of gate layout patterns, being separated from the set of active region layout patterns in the second direction by at least a first distance. The first distance satisfying a first design rule of the set of design rules.

公开(公告)号：US11075164B2

公开(公告)日：2021-07-27

申请号：US16676175

申请日：2019-11-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tung-Heng Hsieh ,  Ting-Wei Chiang ,  Chung-Te Lin ,  Hui-Zhong Zhuang ,  Li-Chun Tien ,  Sheng-Hsiung Wang

IPC: H01L23/528 ,  H01L23/535 ,  H01L27/088 ,  H01L29/40 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/485

Abstract: A semiconductor device includes a substrate having an active region, a first gate structure over a top surface of the substrate, a second gate structure over the top surface of the substrate, a pair of first spacers on each sidewall of the first gate structure, a pair of second spacers on each sidewall of the second gate structure, an insulating layer over at least the first gate structure, a first conductive feature over the active region and a second conductive feature over the substrate. Further, the second gate structure is adjacent to the first gate structure and a top surface of the first conductive feature is coplanar with a top surface of the second conductive feature.

公开(公告)号：US20210202466A1

公开(公告)日：2021-07-01

申请号：US16731387

申请日：2019-12-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shi-Wei Peng ,  Hui-Zhong Zhuang ,  Jiann-Tyng Tzeng ,  Wei-Cheng Lin ,  Guo-Huei Wu

IPC: H01L27/02 ,  H01L23/522

Abstract: A circuit includes a first metal layer having a first first metal layer strip adjacent to a first boundary and a second first metal layer strip adjacent to a second boundary opposite to the first boundary. The first and second first metal layer strips, the first boundary, and the second boundary are parallel to each other. The circuit further includes a second metal layer having a first second metal layer strip and a second second metal layer strip adjacent to the first second metal layer strip. The first second metal layer strip is connected to the first metal layer strip at the first first metal layer strip and the second second metal layer strip is connected to the first metal layer strip at the second first metal layer strip. Each of the first and the second second metal layer strips are parallel to each other.

公开(公告)号：US10734321B2

公开(公告)日：2020-08-04

申请号：US16135684

申请日：2018-09-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Pochun Wang ,  Ting-Wei Chiang ,  Chih-Ming Lai ,  Hui-Zhong Zhuang ,  Jung-Chan Yang ,  Ru-Gun Liu ,  Ya-Chi Chou ,  Yi-Hsiung Lin ,  Yu-Xuan Huang ,  Yu-Jung Chang ,  Guo-Huei Wu ,  Shih-Ming Chang

IPC: H01L29/40 ,  H01L23/535 ,  H01L21/768 ,  H01L27/088 ,  H01L27/092 ,  H01L21/8238 ,  G06F30/39 ,  G06F30/392

Abstract: An integrated circuit includes a set of active regions in a substrate, a first set of conductive structures, a shallow trench isolation (STI) region, a set of gates and a first set of vias. The set of active regions extend in a first direction and is located on a first level. The first set of conductive structures and the STI region extend in at least the first direction or a second direction, is located on the first level, and is between the set of active regions. The STI region is between the set of active regions and the first set of conductive structures. The set of gates extend in the second direction and overlap the first set of conductive structures. The first set of vias couple the first set of conductive structures to the set of gates.

公开(公告)号：US10727177B2

公开(公告)日：2020-07-28

申请号：US16174953

申请日：2018-10-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chung-Te Lin ,  Ting-Wei Chiang ,  Hui-Zhong Zhuang ,  Li-Chun Tien ,  Pin-Dai Sue

IPC: H01L23/522 ,  H01L27/02 ,  H01L27/118

Abstract: A device includes gates and a first conductive segment. A first distance is present between a first gate of the gates and the first conductive segment. A second distance is present between a second gate of the gates and the first conductive segment. The first distance is greater than the second distance.

公开(公告)号：US10685982B2

公开(公告)日：2020-06-16

申请号：US16007973

申请日：2018-06-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Hsueh-Chih Chou ,  Chia Hao Tu ,  Sang Hoo Dhong ,  Lee-Chung Lu ,  Li-Chun Tien ,  Ting-Wei Chiang ,  Hui-Zhong Zhuang

IPC: H01L27/11 ,  H01L27/118 ,  H01L27/02

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a first standard cell; and a second standard cell; wherein a cell width of the first standard cell along a first direction is substantially the same as a cell width of the second standard cell along the first direction, and a cell height of the first standard cell along a second direction perpendicular to the first direction is substantially greater than a cell height of the second standard cell along the second direction.