公开(公告)号：US11450563B2

公开(公告)日：2022-09-20

申请号：US17039390

申请日：2020-09-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Jiun Lin ,  Yu Chao Lin ,  Tung Ying Lee

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: An embodiment is a method including forming an opening in a mask layer, the opening exposing a conductive feature below the mask layer, forming a conductive material in the opening using an electroless deposition process, the conductive material forming a conductive via, removing the mask layer, forming a conformal barrier layer on a top surface and sidewalls of the conductive via, forming a dielectric layer over the conformal barrier layer and the conductive via, removing the conformal barrier layer from the top surface of the conductive via, and forming a conductive line over and electrically coupled to the conductive via.

公开(公告)号：US11444174B2

公开(公告)日：2022-09-13

申请号：US16562416

申请日：2019-09-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kai-Tai Chang ,  Tung Ying Lee ,  Wei-Sheng Yun ,  Tzu-Chung Wang ,  Chia-Cheng Ho ,  Ming-Shiang Lin ,  Tzu-Chiang Chen

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/762 ,  H01L21/306 ,  H01L29/08 ,  H01L27/088 ,  H01L21/3105 ,  H01L21/265 ,  H01L29/10 ,  H01L29/423 ,  H01L21/308

Abstract: A semiconductor device includes a first fin and a second fin in a first direction and aligned in the first direction over a substrate, an isolation insulating layer disposed around lower portions of the first and second fins, a first gate electrode extending in a second direction crossing the first direction and a spacer dummy gate layer, and a source/drain epitaxial layer in a source/drain space in the first fin. The source/drain epitaxial layer is adjacent to the first gate electrode and the spacer dummy gate layer with gate sidewall spacers disposed therebetween, and the spacer dummy gate layer includes one selected from the group consisting of silicon nitride, silicon oxynitride, silicon carbon nitride, and silicon carbon oxynitride.

公开(公告)号：US11205706B2

公开(公告)日：2021-12-21

申请号：US16657873

申请日：2019-10-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Lin Yang ,  Tung Ying Lee ,  Shao-Ming Yu ,  Chao-Ching Cheng ,  Tzu-Chiang Chen ,  Chao-Hsien Huang

IPC: H01L29/49 ,  H01L21/02 ,  H01L21/31 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L21/764 ,  H01L21/311 ,  H01L21/3115 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  B82Y10/00 ,  H01L29/40 ,  H01L29/775

Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. A first insulating layer is formed, in the source/drain space, at least on etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space, thereby forming air gaps between the source/drain epitaxial layer and the first semiconductor layers.

公开(公告)号：US11189522B2

公开(公告)日：2021-11-30

申请号：US16939391

申请日：2020-07-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Hsuan Hsiao ,  Yee-Chia Yeo ,  Tung Ying Lee ,  Chih Chieh Yeh

IPC: H01L21/768 ,  H01L27/088 ,  H01L21/28 ,  H01L29/417 ,  H01L21/8234 ,  H01L27/108 ,  H01L29/78

Abstract: In a method of forming a semiconductor device including a fin field effect transistor (FinFET), a first sacrificial layer is formed over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is patterned, thereby forming an opening. A first liner layer is formed on the isolation insulating layer in a bottom of opening and at least side faces of the patterned first sacrificial layer. After the first liner layer is formed, a dielectric layer is formed in the opening. After the dielectric layer is formed, the patterned first sacrificial layer is removed, thereby forming a contact opening over the source/drain structure. A conductive layer is formed in the contact opening.

公开(公告)号：US20210335676A1

公开(公告)日：2021-10-28

申请号：US17368550

申请日：2021-07-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Ching Cheng ,  Tzu-Chiang Chen ,  Chen-Feng Hsu ,  Yu-Lin Yang ,  Tung Ying Lee ,  Chih Chieh Yeh

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L29/775 ,  H01L29/08 ,  H01L21/8234 ,  B82Y10/00

Abstract: Nanowire devices and fin devices are formed in a first region and a second region of a substrate. To form the devices, alternating layers of a first material and a second material are formed, inner spacers are formed adjacent to the layers of the first material, and then the layers of the first material are removed to form nanowires without removing the layers of the first material within the second region. Gate structures of gate dielectrics and gate electrodes are formed within the first region and the second region in order to form the nanowire devices in the first region and the fin devices in the second region.

公开(公告)号：US20210305508A1

公开(公告)日：2021-09-30

申请号：US17072897

申请日：2020-10-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tung Ying Lee ,  Shao-Ming Yu ,  Yu Chao Lin

IPC: H01L45/00 ,  H01L27/24

Abstract: In an embodiment, a device includes: a first metallization layer over a substrate, the substrate including active devices; a first bit line over the first metallization layer, the first bit line connected to first interconnects of the first metallization layer, the first bit line extending in a first direction, the first direction parallel to gates of the active devices; a first phase-change random access memory (PCRAM) cell over the first bit line; a word line over the first PCRAM cell, the word line extending in a second direction, the second direction perpendicular to the gates of the active devices; and a second metallization layer over the word line, the word line connected to second interconnects of the second metallization layer.

公开(公告)号：US20210167192A1

公开(公告)日：2021-06-03

申请号：US17173090

申请日：2021-02-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Lien Huang ,  Tung Ying Lee

IPC: H01L29/66 ,  H01L21/311 ,  H01L29/78 ,  H01L21/768 ,  H01L21/285 ,  H01L21/306 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/45

Abstract: An integrated circuit structure includes a semiconductor substrate, insulation regions extending into the semiconductor substrate, with the insulation regions including first top surfaces and second top surfaces lower than the first top surfaces, a semiconductor fin over the first top surfaces of the insulation regions, a gate stack on a top surface and sidewalls of the semiconductor fin, and a source/drain region on a side of the gate stack. The source/drain region includes a first portion having opposite sidewalls that are substantially parallel to each other, with the first portion being lower than the first top surfaces and higher than the second top surfaces of the insulation regions, and a second portion over the first portion, with the second portion being wider than the first portion.

公开(公告)号：US10886268B2

公开(公告)日：2021-01-05

申请号：US15429844

申请日：2017-02-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tung Ying Lee ,  Chih Chieh Yeh ,  Tsung-Lin Lee ,  Yee-Chia Yeo ,  Meng-Hsuan Hsiao

IPC: H01L29/78 ,  H01L29/36 ,  H01L29/45 ,  H01L27/088 ,  H01L29/66 ,  H01L29/417 ,  H01L21/8234

Abstract: In a method of forming a semiconductor device including a fin field effect transistor (FinFET), a sacrificial layer is formed over a source/drain structure of a FinFET structure and an isolation insulating layer. A mask pattern is formed over the sacrificial layer. The sacrificial layer and the source/drain structure are patterned by using the mask pattern as an etching mask, thereby forming openings adjacent to the patterned sacrificial layer and source/drain structure. A dielectric layer is formed in the openings. After the dielectric layer is formed, the patterned sacrificial layer is removed to form a contact opening over the patterned source/drain structure. A conductive layer is formed in the contact opening.

公开(公告)号：US10886180B2

公开(公告)日：2021-01-05

申请号：US16426428

申请日：2019-05-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tung Ying Lee ,  Tzu-Chung Wang ,  Kai-Tai Chang ,  Wei-Sheng Yun

IPC: H01L21/8234 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/04 ,  H01L29/78

Abstract: A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes a plurality of fins on a substrate. A fin end spacer is formed on an end surface of each of the plurality of fins. An insulating layer is formed on the plurality of fins. A source/drain epitaxial layer is formed in a source/drain space in each of the plurality of fins. A gate electrode layer is formed on the insulating layer and wrapping around the each channel region. Sidewall spacers are formed on the gate electrode layer.

公开(公告)号：US10825915B2

公开(公告)日：2020-11-03

申请号：US16679934

申请日：2019-11-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tung Ying Lee ,  Shao-Ming Yu

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/786 ,  H01L29/165 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/40 ,  H01L29/775 ,  H01L29/06 ,  B82Y10/00

Abstract: Gate-all-around (GAA) devices and methods for fabricating such are disclosed herein. An exemplary GAA device includes a first semiconductor layer disposed over a substrate. A gate structure is disposed over and wraps a portion of the first semiconductor layer, such that the gate structure separates a source region of the first semiconductor layer and a drain region of the first semiconductor layer. A channel region of the first semiconductor layer is defined between the source region and the drain region. A dielectric layer is disposed adjacent to the first semiconductor layer, where the dielectric layer extends along an entirety of the source region of the first semiconductor layer and an entirety of the drain region of the first semiconductor layer. A second semiconductor layer disposed over the source region of the first semiconductor layer, the drain region of the first semiconductor layer, and the dielectric layer.