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    SEMICONDUCTOR MEMORY STRUCTURE AND FABRICATION METHOD THEREOF
    85.
    发明申请
    SEMICONDUCTOR MEMORY STRUCTURE AND FABRICATION METHOD THEREOF 有权

    公开(公告)号：US20230081533A1

    公开(公告)日：2023-03-16

    申请号：US17502056

    申请日：2021-10-15

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Kuo-Hsing Lee ,  Chien-Liang Wu ,  Wen-Kai Lin ,  Te-Wei Yeh ,  Sheng-Yuan Hsueh ,  Chi-Horn Pai

    IPC: G11C17/16 ,  G11C16/10

    Abstract: A semiconductor memory structure includes a substrate having thereon a transistor forming region and a capacitor forming region. A transistor is disposed on the substrate within the transistor forming region. A capacitor is disposed within the capacitor forming region and electrically coupled to the transistor. A first inter-layer dielectric layer covers the transistor forming region and the capacitor forming region. The first inter-layer dielectric layer surrounds a metal gate of the transistor and a bottom plate of the capacitor. A cap layer is disposed on the first inter-layer dielectric layer. The cap layer has a first thickness within the transistor forming region and a second thickness within the capacitor forming region. The first thickness is greater than the second thickness. The cap layer within the capacitor forming region acts as a capacitor dielectric layer of the capacitor.

    Magnetoresistive random access memory
    86.
    发明授权
    Magnetoresistive random access memory 有权

    公开(公告)号：US11569295B2

    公开(公告)日：2023-01-31

    申请号：US16924169

    申请日：2020-07-08

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Kuo-Hsing Lee ,  Sheng-Yuan Hsueh ,  Te-Wei Yeh ,  Chien-Liang Wu

    IPC: H01L27/22 ,  G11C7/18 ,  H01L43/02

    Abstract: A magnetoresistive random access memory (MRAM) includes a first transistor and a second transistor on a substrate, a source line coupled to a first source/drain region of the first transistor, and a first metal interconnection coupled to a second source/drain region of the first transistor. Preferably, the first metal interconnection is extended to overlap the first transistor and the second transistor and the first metal interconnection further includes a first end coupled to the second source/drain region of the first transistor and a second end coupled to a magnetic tunneling junction (MTJ).

    HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) AND FORMING METHOD THEREOF
    87.
    发明申请
    HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) AND FORMING METHOD THEREOF 有权

    公开(公告)号：US20220173236A1

    公开(公告)日：2022-06-02

    申请号：US17676799

    申请日：2022-02-21

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Kuo-Hsing Lee ,  Yi-Chung Sheng ,  Sheng-Yuan Hsueh ,  Chih-Kai Kang ,  Guan-Kai Huang ,  Chien-Liang Wu

    IPC: H01L29/778 ,  H01L29/66

    Abstract: A high electron mobility transistor (HEMT) includes a carrier transit layer, a carrier supply layer, a main gate, a control gate, a source electrode and a drain electrode. The carrier transit layer is on a substrate. The carrier supply layer is on the carrier transit layer. The main gate and the control gate are on the carrier supply layer. A fluoride ion doped region is formed right below the main gate in the carrier supply layer. The source electrode and the drain electrode are at two opposite sides of the main gate and the control gate, wherein the source electrode is electrically connected to the control gate by a metal interconnect. The present invention also provides a method of forming a high electron mobility transistor (HEMT).

    Semiconductor Device and Method of Forming the Same
    88.
    发明申请
    Semiconductor Device and Method of Forming the Same 有权

    公开(公告)号：US20220123200A1

    公开(公告)日：2022-04-21

    申请号：US17095752

    申请日：2020-11-12

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Kuo-Hsing Lee ,  Chun-Hsien Lin ,  Sheng-Yuan Hsueh

    IPC: H01L43/02 ,  H01L43/12 ,  H01L27/22

    Abstract: The present invention provides a semiconductor device and a method of forming the same, and the semiconductor device includes a substrate, a first interconnect layer and a second interconnect layer. The first interconnect layer is disposed on the substrate, and the first interconnect layer includes a first dielectric layer around a plurality of first magnetic tunneling junction (MTJ) structures. The second interconnect layer is disposed on the first interconnect layer, and the second interconnect layer includes a second dielectric layer around a plurality of second MTJ structures, wherein, the second MTJ structures and the first MTJ structures are alternately arranged along a direction. The semiconductor device may obtain a reduced size of each bit cell under a permissible process window, so as to improve the integration of components.

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