公开(公告)号：US20050181559A1

公开(公告)日：2005-08-18

申请号：US10878051

申请日：2004-06-29

申请人： Katsuaki Natori ,  Koji Yamakawa ,  Hiroyuki Kanaya

发明人： Katsuaki Natori ,  Koji Yamakawa ,  Hiroyuki Kanaya

IPC分类号： H01L21/28 ,  H01L21/02 ,  H01L21/20 ,  H01L21/326 ,  H01L21/336 ,  H01L21/479 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8242 ,  H01L21/8244 ,  H01L21/8246 ,  H01L27/04 ,  H01L27/105 ,  H01L27/115

CPC分类号： H01L27/11502 ,  H01L27/11507 ,  H01L28/57

摘要： Disclosed is a method of manufacturing a semiconductor device, comprising forming a bottom electrode film of a capacitor above a semiconductor substrate, forming a dielectric film of the capacitor on the bottom electrode film, forming a top electrode film of the capacitor on the dielectric film, and forming a hydrogen barrier film after forming the top electrode film, the hydrogen barrier film preventing hydrogen from diffusing into the dielectric film, wherein forming the hydrogen barrier film includes forming an oxide film containing silicon and nitriding the oxide film.

摘要翻译： 公开了一种制造半导体器件的方法，包括在半导体衬底上形成电容器的底部电极膜，在底部电极膜上形成电容器的电介质膜，在电介质膜上形成电容器的顶部电极膜， 在形成顶电极膜之后形成氢阻挡膜，防止氢扩散到电介质膜中的氢阻挡膜，其中形成氢阻挡膜包括形成含硅氧化膜并氮化氧化膜。

公开(公告)号：US20050176199A1

公开(公告)日：2005-08-11

申请号：US10618616

申请日：2003-07-15

申请人： Tohru Ozaki ,  Iwao Kunishima ,  Toyota Morimoto ,  Hiroyuki Kanaya

发明人： Tohru Ozaki ,  Iwao Kunishima ,  Toyota Morimoto ,  Hiroyuki Kanaya

IPC分类号： H01L27/105 ,  H01L21/8246 ,  H01L27/115 ,  H01L21/336

CPC分类号： H01L27/11502 ,  H01L27/11507

摘要： A semiconductor memory device including a memory cell block having a plurality of memory transistors formed on a semiconductor substrate. The memory transistors include first and second impurity-diffused regions and a gate formed therebetween. A plurality of memory cells are also included in the memory cell block and have lower electrodes connected to the first impurity-diffused regions, ferroelectric films formed on the lower electrodes and first upper electrodes formed on the ferroelectric films and connected to the second impurity-diffused regions. Further included are block selecting transistors formed on the semiconductor substrate and being connected to one end of the memory cell block. Second upper electrodes are also formed adjoined to the block selecting transistors and being disconnected from the first upper electrode of the memory cells.

摘要翻译： 一种半导体存储器件，包括具有形成在半导体衬底上的多个存储晶体管的存储单元块。 存储晶体管包括第一和第二杂质扩散区域以及在它们之间形成的栅极。 多个存储单元也包括在存储单元块中，并且具有连接到第一杂质扩散区的下电极，形成在下电极上的铁电膜和形成在铁电体膜上的第一上电极并连接到第二杂质扩散区 地区。 还包括形成在半导体衬底上并连接到存储单元块的一端的块选择晶体管。 第二上电极也形成为与块选择晶体管相邻并且与存储单元的第一上电极断开连接。

公开(公告)号：US20050110062A1

公开(公告)日：2005-05-26

申请号：US10954183

申请日：2004-10-01

申请人： Katsuaki Natori ,  Koji Yamakawa ,  Hiroyuki Kanaya

发明人： Katsuaki Natori ,  Koji Yamakawa ,  Hiroyuki Kanaya

IPC分类号： H01L29/41 ,  H01L21/02 ,  H01L21/768 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/108 ,  H01L29/76

CPC分类号： H01L28/65 ,  H01L21/7687 ,  H01L27/10814 ,  H01L27/10855 ,  H01L28/55

摘要： A semiconductor device comprises a semiconductor substrate including a diffusion area, a capacitor provided above the semiconductor substrate and including a lower electrode, a dielectric film, and an upper electrode, a plug provided between the semiconductor substrate and the capacitor and having a lower end connected to the diffusion area and an upper end connected to the lower electrode, and a dummy plug provided between the semiconductor substrate and the capacitor and having a lower end not connected to the diffusion area and an upper end connected to the lower electrode.

摘要翻译： 一种半导体器件包括：包括扩散区域的半导体衬底，设置在半导体衬底上方并包括下电极，电介质膜和上电极的电容器，设置在半导体衬底和电容器之间并具有下端连接的插头 扩散区域和连接到下电极的上端，以及设置在半导体衬底和电容器之间并具有未连接到扩散区域的下端和连接到下电极的上端的虚拟插头。

公开(公告)号：US06847073B2

公开(公告)日：2005-01-25

申请号：US10648511

申请日：2003-08-27

申请人： Hiroyuki Kanaya

发明人： Hiroyuki Kanaya

IPC分类号： H01L21/02 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/76 ,  H01L29/94 ,  H01L31/113 ,  H01L31/119 ,  H01L31/862

CPC分类号： H01L27/11502 ,  H01L27/11507 ,  H01L28/55

摘要： A semiconductor device includes a MOS transistor, an interlayer insulating film, a contact plug, a capacitor lower electrode, a ferroelectric film and two capacitor upper electrodes. The MOS transistor is formed on a semiconductor substrate. The interlayer insulating film covers the MOS transistor. The contact plug is connected to an impurity diffusion layer of the MOS transistor. The capacitor lower electrode is formed on the contact plug. The two capacitor upper electrodes are formed on the capacitor lower electrode with the ferroelectric film interposed therebetween. A contact area between the contact plug and the capacitor lower electrode is greater than a contact area between each of the two capacitor upper electrodes and the ferroelectric film. At least a part of a gate electrode of the MOS transistor is located just below a region of the contact plug, which region is in contact with the capacitor lower electrode.

摘要翻译： 半导体器件包括MOS晶体管，层间绝缘膜，接触插塞，电容器下电极，铁电体膜和两个电容器上电极。 MOS晶体管形成在半导体衬底上。 层间绝缘膜覆盖MOS晶体管。 接触插塞连接到MOS晶体管的杂质扩散层。 电容器下电极形成在接触插塞上。 两个电容器上电极形成在电容器下电极上，其间插有铁电体膜。 接触插塞和电容器下电极之间的接触面积大于两个电容器上部电极和铁电体膜中的每个之间的接触面积。 MOS晶体管的栅电极的至少一部分位于接触插塞的区域正下方，该区域与电容器下电极接触。

公开(公告)号：US06642563B2

公开(公告)日：2003-11-04

申请号：US09948574

申请日：2001-09-10

申请人： Hiroyuki Kanaya

发明人： Hiroyuki Kanaya

IPC分类号： H01L31119

CPC分类号： H01L27/11502 ,  H01L21/28273 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76829 ,  H01L27/11507 ,  H01L28/57 ,  H01L29/66545 ,  H01L29/78391

摘要： A semiconductor memory including a ferroelectric gate capacitor structure includes an insulating interlayer formed on the surface of a semiconductor substrate. The insulating interlayer includes a hole at a position corresponding to a channel region. In the channel length direction, the hole extends across the channel region. A ferroelectric gate capacitor structure is formed in the hole. The ferroelectric gate capacitor structure includes a dielectric film, ferroelectric film, and upper electrode formed in this order from the substrate side.

公开(公告)号：US5818869A

公开(公告)日：1998-10-06

申请号：US858146

申请日：1997-05-15

申请人： Kazuyuki Miya ,  Roland Go ,  Hiroyuki Kanaya

发明人： Kazuyuki Miya ,  Roland Go ,  Hiroyuki Kanaya

IPC分类号： H04B1/707 ,  H04B1/7073 ,  H04B1/7075 ,  H04B7/26 ,  H04W56/00 ,  H04L7/00

CPC分类号： H04B1/70752 ,  H04B1/70754 ,  H04B1/70757

摘要： A synchronizing method and circuit accurately and stably operates a direct spread spectrum multiple access communication system. A signal transmitted by modulating the spreading code with data at the transmission side is sampled by a signal of n times (n: 1 or larger integer) the clock speed of the spread spectrum signal at the reception side, and the correlation is detected by a digital matched filter. Consequently, the detection output in every sample in the symbol period is compared with the envelope detection output determined in every sampling period, and the sample positions for a specific number of determined samples are stored in the descending order of the output. The number of times of storage of large sample positions in the stored detection output is counted in every symbol period, and the position of the largest number of storage times is detected as the peak position. From this peak position, capturing or holding the symbol period, and setting of the reception window position results.

摘要翻译： 一种同步方法和电路准确稳定地操作直扩扩频多址通信系统。 通过在发送侧用数据调制扩展码发送的信号由接收侧的扩频信号的时钟速度的n倍（n = 1或更大整数）的信号进行采样，并且相关性由 数字匹配滤波器 因此，将符号周期中的每个采样中的检测输出与在每个采样周期中确定的包络检测输出进行比较，并且以输出的降序存储特定数量的确定采样的采样位置。 在每个符号周期中对存储的检测输出中的大样本位置的存储次数进行计数，并且检测最大数量的存储时间的位置作为峰值位置。 从该峰值位置，捕获或保持符号周期，并设置接收窗口位置结果。