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公开(公告)号：US11682727B2
公开(公告)日：2023-06-20
申请号：US17102819
申请日：2020-11-24
发明人： Fujio Masuoka , Nozomu Harada , Yoshiaki Kikuchi
CPC分类号： H01L29/7827 , H01L29/0847 , H01L29/66666 , H01L29/7848 , H01L21/02238 , H01L21/02255 , H01L29/42376 , H01L29/4966 , H01L29/517
摘要： A SiO2 layer is disposed in the bottom portion of a Si pillar and on an i-layer substrate. A gate HfO2 layer 11b is disposed so as to surround the side surface of the Si pillar, and a gate TiN layer is disposed so as to surround the HfO2 layer. P+ layers are disposed that contain an acceptor impurity at a high concentration, serve as a source and a drain, and are simultaneously or separately formed by a selective epitaxial crystal growth method on the exposed side surface of the bottom portion of and on the top portion of the Si pillar. Thus, an SGT is formed on the i-layer substrate.
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公开(公告)号：US11309426B2
公开(公告)日：2022-04-19
申请号：US16580510
申请日：2019-09-24
发明人： Fujio Masuoka , Nozomu Harada
IPC分类号： H01L29/786 , H01L29/423 , H01L21/225 , H01L21/324 , H01L27/092 , H01L29/40 , H01L29/417 , H01L29/66
摘要： An SGT circuit includes a first conductor layer which contains a semiconductor atom, which is in contact with an N+ region and a P+ region of a Si pillar, or a TiN layer, and whose outer circumference is located outside an outer circumference of a SiO2 layer in plan view, and a second conductor layer which contains a metal atom, which is connected to an outer periphery of the first conductor layer, and which extends in a horizontal direction.
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公开(公告)号：US11282958B2
公开(公告)日：2022-03-22
申请号：US16832386
申请日：2020-03-27
发明人： Fujio Masuoka , Nozomu Harada
IPC分类号： H01L29/78 , H01L29/66 , H01L29/423 , H01L21/8238 , H01L29/10 , H01L29/417 , H01L29/786 , H01L21/461 , H01L21/475 , H01L29/06 , H01L29/775
摘要： An SGT is formed that includes Si pillars. The SGT includes WSi2 layers serving as wiring alloy layers and constituted by first alloy regions that are connected to the entire peripheries of impurity regions serving as sources or drains located in lower portions of the Si pillars, are formed in a self-aligned manner with the impurity regions in a tubular shape, and contain the same impurity atom as the impurity regions and a second alloy region that is partly connected to the peripheries of the first alloy regions and contains the same impurity atom as the impurity regions.
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公开(公告)号：US10910039B2
公开(公告)日：2021-02-02
申请号：US16386748
申请日：2019-04-17
发明人： Fujio Masuoka , Masamichi Asano
IPC分类号： G11C11/418 , H01L27/092 , H01L21/8238 , G11C8/08 , G11C8/10 , H01L27/11 , H01L29/423 , G11C5/06 , H01L29/16 , H01L29/78
摘要： A semiconductor device constituting a decoder circuit for memory selection and having a smaller area is provided by using surrounding gate transistors (SGTs), which are vertical transistors. In a decoder circuit formed by a plurality of MOS transistors arranged in m rows and n columns, the MOS transistors that constitute the decoder circuit are arranged on a planar silicon layer formed on a substrate. Each has a structure including a drain, a gate, and a source arranged in a vertical direction, the gate surrounding a semiconductor pillar. The planar silicon layer is formed by a first active region of a first conductivity type and a second active region of a second conductivity type, and the regions are connected to each other via a conductive region formed on the surface of the planar silicon layer. Consequently, a semiconductor device that constitutes a decoder circuit having a smaller area is provided.
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公开(公告)号：US10811535B2
公开(公告)日：2020-10-20
申请号：US15143725
申请日：2016-05-02
发明人： Fujio Masuoka , Hiroki Nakamura
IPC分类号： H01L23/535 , H01L29/78 , H01L29/66 , H01L29/423 , H01L29/786 , H01L29/775 , H01L29/06
摘要： An SGT production method includes a first step of forming a fin-shaped semiconductor layer and a first insulating film; a second step of forming a second insulating film, depositing a first polysilicon, planarizing the first polysilicon, forming a third insulating film, forming a second resist, and etching the third insulating film, the first polysilicon, the second insulating film, and the fin-shaped semiconductor layer to form a pillar-shaped semiconductor layer, a first dummy gate, and a first hard mask; and a third step of forming a fourth insulating film, depositing a second polysilicon, planarizing the second polysilicon, subjecting the second polysilicon to etch back to expose the first hard mask, depositing a sixth insulating film, etching the sixth insulating film to form a second hard mask on a side wall of the first hard mask, and etching the second polysilicon to form a second dummy gate.
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公开(公告)号：US10804397B2
公开(公告)日：2020-10-13
申请号：US15223236
申请日：2016-07-29
发明人： Fujio Masuoka , Hiroki Nakamura
IPC分类号： H01L29/78 , H01L29/66 , H01L29/423 , H01L29/786 , H01L23/535 , H01L29/775 , H01L29/06
摘要： An SGT production method includes a first step of forming a fin-shaped semiconductor layer and a first insulating film; a second step of forming a second insulating film, depositing a first polysilicon, planarizing the first polysilicon, forming a third insulating film, forming a second resist, and etching the third insulating film, the first polysilicon, the second insulating film, and the fin-shaped semiconductor layer to form a pillar-shaped semiconductor layer, a first dummy gate, and a first hard mask; and a third step of forming a fourth insulating film, depositing a second polysilicon, planarizing the second polysilicon, subjecting the second polysilicon to etch back to expose the first hard mask, depositing a sixth insulating film, etching the sixth insulating film to form a second hard mask on a side wall of the first hard mask, and etching the second polysilicon to form a second dummy gate.
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公开(公告)号：US10411021B2
公开(公告)日：2019-09-10
申请号：US15897424
申请日：2018-02-15
发明人： Fujio Masuoka , Hiroki Nakamura
IPC分类号： H01L27/11 , H01L27/02 , H01L29/423 , H01L27/06 , H01L29/78
摘要： A static random access memory (SRAM) device includes an inverter including a ninth first-conductivity-type semiconductor layer formed on a semiconductor substrate; a first pillar-shaped semiconductor layer which is formed on the semiconductor substrate and in which a first first-conductivity-type semiconductor layer, a first body region, a second first-conductivity-type semiconductor layer, a first second-conductivity-type semiconductor layer, a second body region, and a second second-conductivity-type semiconductor layer are formed from the substrate side in that order; a first gate insulating film formed around the first body region; a first gate formed around the first gate insulating film; a second gate insulating film formed around the second body region; a second gate formed around the second gate insulating film; and a first output terminal connected to the second first-conductivity-type semiconductor layer and the first second-conductivity-type semiconductor layer.
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公开(公告)号：US10410932B2
公开(公告)日：2019-09-10
申请号：US16261080
申请日：2019-01-29
发明人： Fujio Masuoka , Nozomu Harada
IPC分类号： H01L21/336 , H01L21/8238 , H01L27/11 , H01L27/092 , H01L29/423 , H01L29/786 , H01L21/768 , H01L23/535
摘要： A method for producing a pillar-shaped semiconductor device includes forming, above a NiSi layer serving as a lower wiring conductor layer and connecting to an N+ layer of an SGT formed within a Si pillar, a first conductor W layer that extends through a NiSi layer serving as an upper wiring conductor layer and connecting to a gate TiN layer and that extends through a NiSi layer serving as an intermediate wiring conductor layer and connecting to an N+ layer; forming an insulating SiO2 layer between the NiSi layer and the W layer; and forming a second conductor W layer so as to surround the W layer and have its bottom at the upper surface layer of the NiSi layer, to achieve connection between the NiSi layer and the NiSi layer.
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公开(公告)号：US10381451B2
公开(公告)日：2019-08-13
申请号：US15788353
申请日：2017-10-19
发明人： Fujio Masuoka , Hiroki Nakamura
IPC分类号： H01L29/423 , H01L29/78 , H01L29/66 , H01L29/778 , H01L29/49 , H01L29/786
摘要： A semiconductor device includes a pillar-shaped semiconductor layer formed on a substrate; a first insulator surrounding the pillar-shaped semiconductor layer; a first gate surrounding the first insulator and made of a metal having a first work function; a second gate surrounding the first insulator and made of a metal having a second work function different from the first work function, the second gate being located below the first gate; a third gate surrounding the first insulator and made of a metal having the first work function, the third gate being located below the second gate; and a fourth gate surrounding the first insulator and made of a metal having the second work function different from the first work function, the fourth gate being located below the third gate. The first gate, the second gate, the third gate, and the fourth gate are electrically connected together.
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公开(公告)号：US10311945B2
公开(公告)日：2019-06-04
申请号：US14886637
申请日：2015-10-19
发明人： Fujio Masuoka , Masamichi Asano
IPC分类号： G11C11/418 , H01L27/092 , H01L21/8238 , G11C8/08 , G11C8/10 , H01L27/11 , G11C5/06 , H01L29/16 , H01L29/423 , H01L29/78
摘要： A semiconductor device constituting a decoder circuit for memory selection and having a smaller area is provided by using surrounding gate transistors (SGTs), which are vertical transistors. In a decoder circuit formed by a plurality of MOS transistors arranged in m rows and n columns, the MOS transistors that constitute the decoder circuit are arranged on a planar silicon layer formed on a substrate. Each has a structure including a drain, a gate, and a source arranged in a vertical direction, the gate surrounding a silicon pillar. The planar silicon layer is formed by a first active region of a first conductivity type and a second active region of a second conductivity type, and the regions are connected to each other via a silicide layer formed on the surface of the planar silicon layer. Consequently, a semiconductor device that constitutes a decoder circuit having a smaller area is provided.
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