公开(公告)号：US07943920B2

公开(公告)日：2011-05-17

申请号：US12836304

申请日：2010-07-14

申请人： Wei-Chih Chien ,  Kuo-Pin Chang ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

发明人： Wei-Chih Chien ,  Kuo-Pin Chang ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

IPC分类号： H01L29/04

CPC分类号： H01L45/04 ,  H01L45/085 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148 ,  H01L45/1625 ,  H01L45/1633 ,  Y10S438/90

摘要： A memory device comprises first and second electrodes with a memory element and a buffer layer located between and electrically coupled to them. The memory element comprises one or more metal oxygen compounds. The buffer layer comprises at least one of an oxide and a nitride. Another memory device comprises first and second electrodes with a memory element and a buffer layer, having a thickness of less than 50 Å, located between and electrically coupled to them. The memory comprises one or more metal oxygen compounds. An example of a method of fabricating a memory device includes forming first and second electrodes. A memory, located between and electrically coupled to the first and the second electrodes, is formed; the memory comprises one or more metal oxygen compounds and the buffer layer comprises at least one of an oxide and a nitride.

摘要翻译： 存储器件包括具有存储元件的第一和第二电极以及位于它们之间并与之电耦合的缓冲层。 记忆元件包括一种或多种金属氧化合物。 缓冲层包括氧化物和氮化物中的至少一种。 另一个存储器件包括具有存储元件和缓冲层的第一和第二电极，其厚度小于50，位于它们之间并与之电耦合。 记忆体包括一种或多种金属氧化合物。 制造存储器件的方法的一个例子包括形成第一和第二电极。 形成位于第一和第二电极之间并电耦合到第一和第二电极的存储器; 存储器包括一种或多种金属氧化合物，并且缓冲层包括氧化物和氮化物中的至少一种。

公开(公告)号：US07816661B2

公开(公告)日：2010-10-19

申请号：US11562122

申请日：2006-11-21

申请人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh

发明人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh

IPC分类号： H01L21/06 ,  H01L47/00

CPC分类号： H01L45/144 ,  G11C13/00 ,  G11C13/0004 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/1293 ,  H01L45/14 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1675

摘要： A memory device includes, a first electrode element, generally planar in form, having an inner contact surface. Then there is a cylindrical cap layer, spaced from the first electrode element, and a phase change element having contact surfaces in contact with the first electrode contact surface and the cap layer, in which the lateral dimension of the phase change element is less than that of the first electrode element and the cylindrical cap layer. A second electrode element extends through the cap layer to make contact with the phase change element. Side walls aligned with the cap layer, composed of dielectric fill material, extend between the first electrode elements and the cap layer, such that the phase change element, the contact surface of the first electrode element and the side walls define a gas-filled thermal isolation cell adjacent the phase change element.

摘要翻译： 存储器件包括：第一电极元件，其大体呈平面形式，具有内部接触表面。 然后存在与第一电极元件间隔开的圆柱形盖层，以及具有与第一电极接触表面和盖层接触的接触表面的相变元件，其中相变元件的横向尺寸小于 的第一电极元件和圆柱形盖层。 第二电极元件延伸穿过盖层以与相变元件接触。 与介电填充材料构成的盖层对准的侧壁在第一电极元件和盖层之间延伸，使得相变元件，第一电极元件的接触表面和侧壁限定气体充满的热 隔离单元邻近相变元件。

公开(公告)号：US20100216279A1

公开(公告)日：2010-08-26

申请号：US12715888

申请日：2010-03-02

申请人： Erh-kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh

发明人： Erh-kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh

IPC分类号： H01L21/16 ,  H01L21/3205

CPC分类号： G11C13/0016 ,  G11C11/5664 ,  G11C11/5678 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0014 ,  H01L45/04 ,  H01L45/124 ,  H01L45/146 ,  H01L45/1633

摘要： A method and structure of a bistable resistance random access memory comprise a plurality of programmable resistance random access memory cells where each programmable resistance random access memory cell includes multiple memory members for performing multiple bits for each memory cell. The bistable RRAM includes a first resistance random access member connected to a second resistance random access member through interconnect metal liners and metal oxide strips. The first resistance random access member has a first resistance value Ra, which is determined from the thickness of the first resistance random access member based on the deposition of the first resistance random access member. The second resistance random access member has a second resistance value Rb, which is determined from the thickness of the second resistance random access member based on the deposition of the second resistance random access member.

摘要翻译： 双稳态电阻随机存取存储器的方法和结构包括多个可编程电阻随机存取存储单元，其中每个可编程电阻随机存取存储单元包括用于为每个存储单元执行多位的多个存储器构件。 双稳态RRAM包括通过互连金属衬垫和金属氧化物条连接到第二电阻随机存取构件的第一电阻随机存取构件。 第一电阻随机存取构件具有基于第一电阻随机存取构件的沉积从第一电阻随机存取构件的厚度确定的第一电阻值Ra。 第二电阻随机存取部件具有基于第二电阻随机存取部件的沉积从第二电阻随机存取部件的厚度确定的第二电阻值Rb。

公开(公告)号：US07777215B2

公开(公告)日：2010-08-17

申请号：US12176183

申请日：2008-07-18

申请人： Wei-Chih Chien ,  Kuo-Pin Chang ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

发明人： Wei-Chih Chien ,  Kuo-Pin Chang ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

IPC分类号： H01L47/00

CPC分类号： H01L45/04 ,  H01L45/085 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148 ,  H01L45/1625 ,  H01L45/1633 ,  Y10S438/90

摘要： A memory device comprises first and second electrodes with a memory element and a buffer layer located between and electrically coupled to them. The memory element comprises one or more metal oxygen compounds. The buffer layer comprises at least one of an oxide and a nitride. Another memory device comprises first and second electrodes with a memory element and a buffer layer, having a thickness of less than 50 Å, located between and electrically coupled to them. The memory comprises one or more metal oxygen compounds. An example of a method of fabricating a memory device includes forming first and second electrodes. A memory, located between and electrically coupled to the first and the second electrodes, is formed; the memory comprises one or more metal oxygen compounds and the buffer layer comprises at least one of an oxide and a nitride.

摘要翻译： 存储器件包括具有存储元件的第一和第二电极以及位于它们之间并与之电耦合的缓冲层。 记忆元件包括一种或多种金属氧化合物。 缓冲层包括氧化物和氮化物中的至少一种。 另一个存储器件包括具有存储元件和缓冲层的第一和第二电极，其厚度小于50，位于它们之间并与之电耦合。 记忆体包括一种或多种金属氧化合物。 制造存储器件的方法的一个例子包括形成第一和第二电极。 形成位于第一和第二电极之间并电耦合到第一和第二电极的存储器; 存储器包括一种或多种金属氧化合物，并且缓冲层包括氧化物和氮化物中的至少一种。

公开(公告)号：US07718989B2

公开(公告)日：2010-05-18

申请号：US11617542

申请日：2006-12-28

申请人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh

发明人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh

IPC分类号： H01L29/02

CPC分类号： H01L45/122 ,  G11C11/5678 ,  G11C13/0004 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1683

摘要： A memory cell device has a bottom electrode and a top electrode, a plug of memory material in contact with the bottom electrode, and a cup-shaped conductive member having a rim that contacts the top electrode and an opening in the bottom that contacts the memory material. Accordingly, the conductive path in the memory cells passes from the top electrode through the conductive cup-shaped member, and through the plug of phase change material to the bottom electrode. Also, methods for making the memory cell device include steps of forming a bottom electrode island including an insulative element and a stop element over a bottom electrode, forming a separation layer surrounding the island, removing the stop element to form a hole over the insulative element in the separation layer, forming a conductive film in the hole and an insulative liner over conductive film, etching to form a cup-shaped conductive film having a rim and to form an opening through the insulative liner and the bottom of the cup-shaped conductive film to the surface of the bottom electrode, forming a plug of phase change memory material in the opening, and forming a top electrode in contact with the rim of the cup-shaped conductive film.

摘要翻译： 存储单元装置具有底部电极和顶部电极，与底部电极接触的存储器材料的插头以及具有接触顶部电极的边缘和接触存储器的底部开口的杯形导电构件 材料。 因此，存储单元中的导电路径从顶部电极通过导电杯状构件，并通过相变材料的塞子到达底部电极。 此外，用于制造存储单元器件的方法包括在底部电极上形成包括绝缘元件和止动元件的底部电极岛的步骤，形成围绕岛的分离层，去除止动元件以在绝缘元件上方形成孔 在分离层中，在孔中形成导电膜，在导电膜上形成绝缘衬垫，进行蚀刻以形成具有边缘的杯形导电膜，并且通过绝缘衬垫和杯状导电体的底部形成开口 在底部电极的表面形成薄膜，在开口中形成相变记忆材料塞，形成与杯状导电膜的边缘接触的顶部电极。

公开(公告)号：US07527985B2

公开(公告)日：2009-05-05

申请号：US11552327

申请日：2006-10-24

申请人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh

发明人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh

IPC分类号： H01L21/8239

CPC分类号： H01L45/04 ,  G11C11/5678 ,  G11C13/0004 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1625 ,  H01L45/1675

摘要： A method for manufacturing a memory device comprises patterning a dielectric layer and a conductive layer to align near the center of the top surface of a first contact drain plug and near the center of the top surface of a second contact drain plug. A first electrode is formed on the right sidewalls of the patterned dielectric layer and the conductive layer. A sidewall insulating member has a first sidewall surface and a second sidewall surface where the first sidewall surface of the sidewall insulating member is in contact with a sidewall of the first electrode. A second electrode is formed by depositing an electrode layer overlying the top surface of the sidewall insulating member and the second sidewall of the insulating member and isotropically etching the electrode layer to form the second electrode.

摘要翻译： 一种用于制造存储器件的方法包括使电介质层和导电层图案化以在第一接触排放塞的顶表面的中心附近并且靠近第二接触排放塞的顶表面的中心。 第一电极形成在图案化电介质层和导电层的右侧壁上。 侧壁绝缘构件具有第一侧壁表面和第二侧壁表面，其中侧壁绝缘构件的第一侧壁表面与第一电极的侧壁接触。 第二电极通过沉积覆盖侧壁绝缘构件的顶表面和绝缘构件的第二侧壁的电极层而形成，并且各向同性地蚀刻电极层以形成第二电极。

公开(公告)号：US20090020740A1

公开(公告)日：2009-01-22

申请号：US12176183

申请日：2008-07-18

申请人： Wei-Chih CHIEN ,  Kuo-Pin Chang ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

发明人： Wei-Chih CHIEN ,  Kuo-Pin Chang ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

IPC分类号： H01L47/00 ,  H01L21/00

CPC分类号： H01L45/04 ,  H01L45/085 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148 ,  H01L45/1625 ,  H01L45/1633 ,  Y10S438/90

摘要： A memory device comprises first and second electrodes with a memory element and a buffer layer located between and electrically coupled to them. The memory element comprises one or more metal oxygen compounds. The buffer layer comprises at least one of an oxide and a nitride. Another memory device comprises first and second electrodes with a memory element and a buffer layer, having a thickness of less than 50 Å, located between and electrically coupled to them. The memory comprises one or more metal oxygen compounds. An example of a method of fabricating a memory device includes forming first and second electrodes. A memory, located between and electrically coupled to the first and the second electrodes, is formed; the memory comprises one or more metal oxygen compounds and the buffer layer comprises at least one of an oxide and a nitride.

摘要翻译： 存储器件包括具有存储元件的第一和第二电极以及位于它们之间并与之电耦合的缓冲层。 记忆元件包括一种或多种金属氧化合物。 缓冲层包括氧化物和氮化物中的至少一种。 另一个存储器件包括具有存储元件和缓冲层的第一和第二电极，其厚度小于50，位于它们之间并与之电耦合。 记忆体包括一种或多种金属氧化合物。 制造存储器件的方法的一个例子包括形成第一和第二电极。 形成位于第一和第二电极之间并电耦合到第一和第二电极的存储器; 存储器包括一种或多种金属氧化合物，并且缓冲层包括氧化物和氮化物中的至少一种。

公开(公告)号：US20080096341A1

公开(公告)日：2008-04-24

申请号：US11552327

申请日：2006-10-24

申请人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh

发明人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh

IPC分类号： H01L21/8238 ,  H01L21/20 ,  H01L21/00 ,  H01L21/8244

CPC分类号： H01L45/04 ,  G11C11/5678 ,  G11C13/0004 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1625 ,  H01L45/1675

摘要： A method for manufacturing a memory device comprises patterning a dielectric layer and a conductive layer to align near the center of the top surface of a first contact drain plug and near the center of the top surface of a second contact drain plug. A first electrode is formed on the right sidewalls of the patterned dielectric layer and the conductive layer. A sidewall insulating member has a first sidewall surface and a second sidewall surface where the first sidewall surface of the sidewall insulating member is in contact with a sidewall of the first electrode. A second electrode is formed by depositing an electrode layer overlying the top surface of the sidewall insulating member and the second sidewall of the insulating member and isotropically etching the electrode layer to form the second electrode.

摘要翻译： 一种用于制造存储器件的方法包括使电介质层和导电层图案化以在第一接触排放塞的顶表面的中心附近并且靠近第二接触排放塞的顶表面的中心。 第一电极形成在图案化电介质层和导电层的右侧壁上。 侧壁绝缘构件具有第一侧壁表面和第二侧壁表面，其中侧壁绝缘构件的第一侧壁表面与第一电极的侧壁接触。 第二电极通过沉积覆盖侧壁绝缘构件的顶表面和绝缘构件的第二侧壁的电极层而形成，并且各向同性地蚀刻电极层以形成第二电极。

公开(公告)号：US20080094875A1

公开(公告)日：2008-04-24

申请号：US11552464

申请日：2006-10-24

申请人： ChiaHua Ho ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

发明人： ChiaHua Ho ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

IPC分类号： G11C11/00

CPC分类号： G11C17/165 ,  B82Y10/00 ,  G11C11/5664 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0014 ,  G11C13/0016 ,  G11C13/0069 ,  G11C17/16 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/77

摘要： A method is described for operating a bistable resistance random access memory having two memory layer stacks that are aligned in series is disclosed. The bistable resistance random access memory comprises two memory layer stacks per memory cell, the bistable resistance random access memory operates in four logic states, a logic “00” state, a logic “01” state, a logic “10” state and a logic “11” state. The relationship between the four different logic states can be represented mathematically by the two variables n and f and a resistance R. The logic “0” state is represented by a mathematical expression (1+f)R. The logic “1” state is represented by a mathematical expression (n+f)R. The logic “2” state is represented by a mathematical expression (1+nf)R. The logic “3” state is represented by a mathematical expression n(1+f)R.

摘要翻译： 描述了一种用于操作具有串联排列的两个存储层堆叠的双稳态电阻随机存取存储器的方法。 双稳态电阻随机存取存储器包括每个存储单元的两个存储层堆栈，双稳态电阻随机存取存储器以四个逻辑状态，逻辑“00”状态，逻辑“01”状态，逻辑“10”状态和逻辑 “11”状态。 四个不同逻辑状态之间的关系可以由两个变量n和f以及电阻R在数学上表示。逻辑“0”状态由数学表达式（1 + f）R表示。 逻辑“1”状态由数学表达式（n + f）R表示。 逻辑“2”状态由数学表达式（1 + nf）R表示。 逻辑“3”状态由数学表达式n（1 + f）R表示。

公开(公告)号：US20070158633A1

公开(公告)日：2007-07-12

申请号：US11463824

申请日：2006-08-10

申请人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh

发明人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh

IPC分类号： H01L47/00

CPC分类号： H01L45/06 ,  H01L45/1233 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/1683

摘要： A non-volatile method with a self-aligned RRAM element. The method includes a lower electrode element, generally planar in form, having an inner contact surface. At the top of the device is a upper electrode element, spaced from the lower electrode element. A containment structure extends between the upper electrode element and the lower electrode element, and this element includes a sidewall spacer element having an inner surface defining a generally funnel-shaped central cavity, terminating at a terminal edge to define a central aperture; and a spandrel element positioned between the sidewall spacer element and the lower electrode, having an inner surface defining a thermal isolation cell, the spandrel inner walls being spaced radially outward from the sidewall spacer terminal edge, such that the sidewall spacer terminal edge projects radially inward from the spandrel element inner surface. ARRAM element extends between the lower electrode element and the upper electrode, occupying at least a portion of the sidewall spacer element central cavity and projecting from the sidewall spacer terminal edge toward and making contact with the lower electrode. In this manner, the spandrel element inner surface is spaced from the RRAM element to define a thermal isolation cell adjacent the RRAM element.

摘要翻译： 具有自对准RRAM元素的非易失性方法。 该方法包括具有内部接触表面的大体平面形状的下部电极元件。 在装置的顶部是与下部电极元件间隔开的上部电极元件。 容纳结构在上电极元件和下电极元件之间延伸，并且该元件包括侧壁间隔元件，其具有限定大致漏斗形中心腔的内表面，终止于端边缘以限定中心孔; 以及位于所述侧壁间隔元件和所述下电极之间的突出元件，具有限定了热隔离单元的内表面，所述凸起内壁与所述侧壁间隔件终端边缘径向向外间隔开，使得所述侧壁间隔件末端边缘径向向内突出 从弹簧元件内表面。 ARRAM元件在下电极元件和上电极之间延伸，占据侧壁间隔元件中心空腔的至少一部分并且从侧壁间隔件终端边缘朝向和与下电极接触。 以这种方式，伞形元件内表面与RRAM元件间隔开以限定与RRAM元件相邻的热隔离单元。