公开(公告)号：US06801465B2

公开(公告)日：2004-10-05

申请号：US10461293

申请日：2003-06-13

申请人： Dinesh Somasekhar ,  Yibin Ye ,  Fatih Hamzaoglu ,  Vivek K. De

发明人： Dinesh Somasekhar ,  Yibin Ye ,  Fatih Hamzaoglu ,  Vivek K. De

IPC分类号： G11C700

CPC分类号： G11C7/12

摘要： An apparatus is described having a plurality of storage cells coupled between a first bit line and a second bit line. The apparatus also has a first transistor that pre-charges the first bit line and provides a first supply of current for one or more leakage currents drawn from the first bit line by any of the plurality of storage cells. The apparatus also has a second transistor that pre-charges the second bit line and provides a second supply of current for one or more leakage currents drawn from the second bit line by any of the plurality of storage cells.

摘要翻译： 描述了具有耦合在第一位线和第二位线之间的多个存储单元的装置。 该装置还具有第一晶体管，其对第一位线进行预充电，并为多个存储单元中的任何一个提供从第一位线提取的一个或多个泄漏电流的第一电流。 该装置还具有第二晶体管，其对第二位线进行预充电并且为多个存储单元中的任一个提供从第二位线提取的一个或多个泄漏电流的第二电流供应。

公开(公告)号：US06608786B2

公开(公告)日：2003-08-19

申请号：US09823575

申请日：2001-03-30

申请人： Dinesh Somasekhar ,  Yibin Ye ,  Fatih Hamzaoglu ,  Vivek K. De

发明人： Dinesh Somasekhar ,  Yibin Ye ,  Fatih Hamzaoglu ,  Vivek K. De

IPC分类号： G11C700

CPC分类号： G11C7/12

摘要： An apparatus is described having a plurality of storage cells coupled between a first bit line and a second bit line. The apparatus also has a first transistor that pre-charges the first bit line and provides a first supply of current for one or more leakage currents drawn from the first bit line by any of the plurality of storage cells. The apparatus also has a second transistor that pre-charges the second bit line and provides a second supply of current for one or more leakage currents drawn from the second bit line by any of the plurality of storage cells.

公开(公告)号：US07602257B2

公开(公告)日：2009-10-13

申请号：US11641006

申请日：2006-12-19

申请人： Gerhard Schrom ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Peter Hazucha ,  Sung Tae Moon ,  Tanay Karnik

发明人： Gerhard Schrom ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Peter Hazucha ,  Sung Tae Moon ,  Tanay Karnik

IPC分类号： H03B27/00

CPC分类号： H03K5/151 ,  H03K3/0315 ,  H03K5/133 ,  H03K7/08 ,  H03K2005/00058 ,  H04L25/4902

摘要： A signal generating circuit is provided. The signal generating circuit may include a plurality of delay circuits coupled to provide a plurality of control signals, a weighted-sum circuit to receive the plurality of control signals and to provide an output analog signal, and a comparator circuit to compare the output analog signal with a voltage and to provide a pulse width modulated (PWM) signal based on the comparison.

摘要翻译： 提供信号发生电路。 信号发生电路可以包括耦合以提供多个控制信号的多个延迟电路，用于接收多个控制信号并提供输出模拟信号的加权和电路，以及比较器电路，用于比较输出模拟信号 并提供基于比较的脉宽调制（PWM）信号。

公开(公告)号：US20080143407A1

公开(公告)日：2008-06-19

申请号：US11641006

申请日：2006-12-19

申请人： Gerhard Schrom ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Peter Hazucha ,  Sung Tae Moon ,  Tanay Karnik

发明人： Gerhard Schrom ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Peter Hazucha ,  Sung Tae Moon ,  Tanay Karnik

IPC分类号： H03K7/08

CPC分类号： H03K5/151 ,  H03K3/0315 ,  H03K5/133 ,  H03K7/08 ,  H03K2005/00058 ,  H04L25/4902

摘要： Embodiments of a signal generating circuit are generally described herein. Other embodiments may be described and claimed.

摘要翻译： 本文一般地描述信号发生电路的实施例。 可以描述和要求保护其他实施例。

公开(公告)号：US20130275935A1

公开(公告)日：2013-10-17

申请号：US13446418

申请日：2012-04-13

申请人： Mahbub Rashed ,  David Doman ,  Dinesh Somasekhar ,  Yan Wang ,  Yunfei Deng ,  Navneet Jain ,  Jongwook Kye ,  Ali Keshavarzi ,  Subramani Kengeri ,  Suresh Venkatesan

发明人： Mahbub Rashed ,  David Doman ,  Dinesh Somasekhar ,  Yan Wang ,  Yunfei Deng ,  Navneet Jain ,  Jongwook Kye ,  Ali Keshavarzi ,  Subramani Kengeri ,  Suresh Venkatesan

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F17/5031 ,  G06F2217/84

摘要： An approach for providing timing-closed FinFET designs from planar designs is disclosed. Embodiments include: receiving one or more planar cells associated with a planar design; generating an initial FinFET design corresponding to the planar design based on the planar cells and a FinFET model; and processing the initial FinFET design to provide a timing-closed FinFET design. Other embodiments include: determining a race condition associated with a path of the initial FinFET design based on a timing analysis of the initial FinFET design; and increasing delay associated with the path to resolve hold violations associated with the race condition, wherein the processing of the initial FinFET design is based on the delay increase.

摘要翻译： 公开了一种从平面设计提供定时关闭的FinFET设计的方法。 实施例包括：接收与平面设计相关联的一个或多个平面单元; 基于平面单元和FinFET模型产生对应于平面设计的初始FinFET设计; 并处理初始FinFET设计以提供定时关闭的FinFET设计。 其他实施例包括：基于初始FinFET设计的时序分析确定与初始FinFET设计的路径相关联的竞争条件; 以及与解决与竞争条件相关联的持续违规的路径相关联的增加的延迟，其中初始FinFET设计的处理基于延迟增加。

公开(公告)号：US08689154B2

公开(公告)日：2014-04-01

申请号：US13446418

申请日：2012-04-13

申请人： Mahbub Rashed ,  David Doman ,  Dinesh Somasekhar ,  Yan Wang ,  Yunfei Deng ,  Navneet Jain ,  Jongwook Kye ,  Ali Keshavarzi ,  Subramani Kengeri ,  Suresh Venkatesan

发明人： Mahbub Rashed ,  David Doman ,  Dinesh Somasekhar ,  Yan Wang ,  Yunfei Deng ,  Navneet Jain ,  Jongwook Kye ,  Ali Keshavarzi ,  Subramani Kengeri ,  Suresh Venkatesan

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F17/5031 ,  G06F2217/84

摘要： An approach for providing timing-closed FinFET designs from planar designs is disclosed. Embodiments include: receiving one or more planar cells associated with a planar design; generating an initial FinFET design corresponding to the planar design based on the planar cells and a FinFET model; and processing the initial FinFET design to provide a timing-closed FinFET design. Other embodiments include: determining a race condition associated with a path of the initial FinFET design based on a timing analysis of the initial FinFET design; and increasing delay associated with the path to resolve hold violations associated with the race condition, wherein the processing of the initial FinFET design is based on the delay increase.

摘要翻译： 公开了一种从平面设计提供定时关闭的FinFET设计的方法。 实施例包括：接收与平面设计相关联的一个或多个平面单元; 基于平面单元和FinFET模型产生对应于平面设计的初始FinFET设计; 并处理初始FinFET设计以提供定时关闭的FinFET设计。 其他实施例包括：基于初始FinFET设计的时序分析确定与初始FinFET设计的路径相关联的竞争条件; 以及与解决与竞争条件相关联的持续违规的路径相关联的增加的延迟，其中初始FinFET设计的处理基于延迟增加。

公开(公告)号：US20080237675A1

公开(公告)日：2008-10-02

申请号：US11731543

申请日：2007-03-29

申请人： Brian S. Doyle ,  Roberts S. Chau ,  Suman Datta ,  Vivek De ,  Ali Keshavarzi ,  Dinesh Somasekhar

发明人： Brian S. Doyle ,  Roberts S. Chau ,  Suman Datta ,  Vivek De ,  Ali Keshavarzi ,  Dinesh Somasekhar

IPC分类号： H01L27/108 ,  H01L21/20 ,  H01L29/92

CPC分类号： H01L28/91 ,  H01L27/10852 ,  H01L29/785

摘要： A capacitor includes a substrate (110, 210), a first electrically insulating layer (120, 220) over the substrate, and a fin (130, 231) including a semiconducting material (135) over the first electrically insulating layer. A first electrically conducting layer (140, 810) is located over the first electrically insulating layer and adjacent to the fin. A second electrically insulating layer (150, 910) is located adjacent to the first electrically conducting layer, and a second electrically conducting layer (160, 1010) is located adjacent to the second electrically insulating layer. The first and second electrically conducting layers together with the second electrically insulating layer form a metal-insulator-metal stack that greatly increases the capacitance area of the capacitor. In one embodiment the capacitor is formed using what may be referred to as a removable metal gate (RMG) approach.

摘要翻译： 电容器包括衬底（110,210），在衬底上方的第一电绝缘层（120,220）以及在第一电绝缘层上包括半导体材料（135）的翅片（130,231）。 第一导电层（140,810）位于第一电绝缘层上并且邻近鳍片。 第二电绝缘层（150,910）位于第一导电层附近，并且第二导电层（160,1010）位于第二电绝缘层附近。 第一和第二导电层与第二电绝缘层一起形成金属 - 绝缘体 - 金属叠层，其大大增加了电容器的电容面积。 在一个实施例中，使用可被称为可拆卸金属门（RMG）方法形成电容器。

公开(公告)号：US08138042B2

公开(公告)日：2012-03-20

申请号：US12967238

申请日：2010-12-14

申请人： Brian S. Doyle ,  Robert S. Chau ,  Suman Datta ,  Vivek De ,  Ali Keshavarzi ,  Dinesh Somasekhar

发明人： Brian S. Doyle ,  Robert S. Chau ,  Suman Datta ,  Vivek De ,  Ali Keshavarzi ,  Dinesh Somasekhar

IPC分类号： H01L27/108

CPC分类号： H01L28/91 ,  H01L27/10852 ,  H01L29/785

摘要： A capacitor includes a substrate (110, 210), a first electrically insulating layer (120, 220) over the substrate, and a fin (130, 231) including a semiconducting material (135) over the first electrically insulating layer. A first electrically conducting layer (140, 810) is located over the first electrically insulating layer and adjacent to the fin. A second electrically insulating layer (150, 910) is located adjacent to the first electrically conducting layer, and a second electrically conducting layer (160, 1010) is located adjacent to the second electrically insulating layer. The first and second electrically conducting layers together with the second electrically insulating layer form a metal-insulator-metal stack that greatly increases the capacitance area of the capacitor. In one embodiment the capacitor is formed using what may be referred to as a removable metal gate (RMG) approach.

摘要翻译： 电容器包括衬底（110,210），在衬底上方的第一电绝缘层（120,220）以及在第一电绝缘层上包括半导体材料（135）的翅片（130,231）。 第一导电层（140,810）位于第一电绝缘层上并且邻近鳍片。 第二电绝缘层（150,910）位于第一导电层附近，并且第二导电层（160,1010）位于第二电绝缘层附近。 第一和第二导电层与第二电绝缘层一起形成金属 - 绝缘体 - 金属叠层，其大大增加了电容器的电容面积。 在一个实施例中，使用可被称为可拆卸金属门（RMG）方法形成电容器。

公开(公告)号：US20110079837A1

公开(公告)日：2011-04-07

申请号：US12967238

申请日：2010-12-14

申请人： Brian S. Doyle ,  Robert S. Chau ,  Suman Datta ,  Vivek De ,  Ali Keshavarzi ,  Dinesh Somasekhar

发明人： Brian S. Doyle ,  Robert S. Chau ,  Suman Datta ,  Vivek De ,  Ali Keshavarzi ,  Dinesh Somasekhar

IPC分类号： H01L27/108 ,  H01L21/8242

CPC分类号： H01L28/91 ,  H01L27/10852 ,  H01L29/785

摘要： A capacitor includes a substrate (110, 210), a first electrically insulating layer (120, 220) over the substrate, and a fin (130, 231) including a semiconducting material (135) over the first electrically insulating layer. A first electrically conducting layer (140, 810) is located over the first electrically insulating layer and adjacent to the fin. A second electrically insulating layer (150, 910) is located adjacent to the first electrically conducting layer, and a second electrically conducting layer (160, 1010) is located adjacent to the second electrically insulating layer. The first and second electrically conducting layers together with the second electrically insulating layer form a metal-insulator-metal stack that greatly increases the capacitance area of the capacitor. In one embodiment the capacitor is formed using what may be referred to as a removable metal gate (RMG) approach.

摘要翻译： 电容器包括衬底（110,210），在衬底上方的第一电绝缘层（120,220）以及在第一电绝缘层上包括半导体材料（135）的翅片（130,231）。 第一导电层（140,810）位于第一电绝缘层上并且邻近鳍片。 第二电绝缘层（150,910）位于第一导电层附近，并且第二导电层（160,1010）位于第二电绝缘层附近。 第一和第二导电层与第二电绝缘层一起形成金属 - 绝缘体 - 金属叠层，其大大增加了电容器的电容面积。 在一个实施例中，使用可被称为可拆卸金属门（RMG）方法形成电容器。

公开(公告)号：US20080237678A1

公开(公告)日：2008-10-02

申请号：US11729192

申请日：2007-03-27

申请人： Suman Datta ,  Jack T. Kavalieros ,  Brian S. Doyle ,  Dinesh Somasekhar ,  Ali Keshavarzi

发明人： Suman Datta ,  Jack T. Kavalieros ,  Brian S. Doyle ,  Dinesh Somasekhar ,  Ali Keshavarzi

IPC分类号： H01L27/108 ,  H01L21/336

CPC分类号： H01L27/10873 ,  H01L27/10826 ,  H01L29/785

摘要： An on-chip memory cell comprises a tri-gate access transistor (145) and a tri-gate capacitor (155). The on-chip memory cell may be an embedded DRAM on a three-dimensional tri-gate transistor and capacitor structures which is fully compatible with existing tri-gate logic transistor fabrication process. Embodiments of the invention use the high fin aspect ratio and inherently superior surface area of the tri-gate transistors to replace the “trench” capacitor in a commodity DRAM with an inversion mode tri-gate capacitor. The tall sidewalls of the tri-gate transistor provide large enough surface area to provide storage capacitance in a small cell area.

摘要翻译： 片上存储单元包括三栅极存取晶体管（145）和三栅极电容器（155）。 片上存储器单元可以是三维三栅晶体管上的嵌入式DRAM和与现有三栅逻辑晶体管制造工艺完全兼容的电容器结构。 本发明的实施例使用三栅极晶体管的高翅片长宽比和固有优越的表面积来替代具有反向模式三栅极电容器的商品DRAM中的“沟槽”电容器。 三栅极晶体管的高侧壁提供足够大的表面积，以在小单元区域中提供存储电容。