公开(公告)号：US20120131419A1

公开(公告)日：2012-05-24

申请号：US13365064

申请日：2012-02-02

申请人： Yutaka Ito ,  Adrian J. Drexler

发明人： Yutaka Ito ,  Adrian J. Drexler

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： G11C7/1006 ,  G06F11/106 ,  G11C11/4096 ,  G11C2207/104

摘要： Data bits stored in memory cells are recognized by an ECC generator as data bit strings in a first direction and data bit strings in a second direction such that each data bit string in the first direction and each data bit string in the second direction share one data bit in common. The ECC controller identifies a data bit string in the first direction having more than one data bit in error based on a respective correction code in the first direction and identifies a data bit string in the second direction having more than one data bit in error based on a respective correction code in the second direction, and causes the data bit shared by the identified data bit string in the first direction and the identified data bit string in the second direction to be changed.

摘要翻译： 存储在存储器单元中的数据位由ECC产生器识别为第一方向上的数据位串和第二方向上的数据位串，使得第一方向上的每个数据位串和第二方向上的每个数据位串共享一个数据 有点共同点。 ECC控制器基于第一方向上的相应校正码来识别具有多于一个错误数据位的第一方向上的数据位串，并且基于第二方向识别具有错误的多于一个数据位的数据位串，基于 相应的校正码在第二方向上，并且使由第一方向上的识别数据位串共享的数据位和第二方向上的识别数据位串变化。

公开(公告)号：US20110299353A1

公开(公告)日：2011-12-08

申请号：US13213949

申请日：2011-08-19

申请人： Yutaka Ito ,  Masayoshi Nomura ,  Keiichiro Abe

发明人： Yutaka Ito ,  Masayoshi Nomura ,  Keiichiro Abe

IPC分类号： G11C5/14

CPC分类号： G11C5/14 ,  G11C5/147 ,  G11C5/148 ,  G11C7/20 ,  G11C11/406 ,  G11C11/4072 ,  G11C11/4074 ,  G11C2211/4067 ,  G11C2211/4068

摘要： Some embodiments include a voltage generator to generate a voltage to apply to a line used to access a memory cell of a memory device in which the voltage is applied to the line when the memory cell is not being accessed, and a power controller to cause the voltage to change during a time interval after a refresh operation of the memory device. Other embodiments including additional apparatus, systems, and methods are disclosed.

摘要翻译： 一些实施例包括电压发生器，用于产生电压以施加到用于访问存储器件的存储器单元的线，其中在存储器单元未被访问时将电压施加到线路;以及功率控制器， 电压在存储器件的刷新操作之后的时间间隔期间改变。 公开了包括附加装置，系统和方法的其它实施例。

公开(公告)号：US08042022B2

公开(公告)日：2011-10-18

申请号：US11716199

申请日：2007-03-08

申请人： Yutaka Ito ,  Takuya Nakanishi

发明人： Yutaka Ito ,  Takuya Nakanishi

IPC分类号： G11C11/406 ,  G11C29/00

CPC分类号： G06F11/106 ,  H03M13/15 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/19 ,  H03M13/23 ,  H03M13/2957

摘要： Methods, apparatuses and systems are disclosed for preserving, verifying, and correcting data in DRAM device during a power-saving mode. In the power-saving mode, memory cells in the DRAM device may be refreshed using a self-refresh operation. This self-refresh operation may allow bit errors to occur in the DRAM device. However, by employing error correction coding (ECC), embodiments of the present invention may detect and correct these potential errors that may occur in the power-saving mode. Furthermore, a partial ECC check cycle is employed to check and correct a sub-set of the memory cells during a periodic self-refresh process that occurs during the power-saving mode.

摘要翻译： 公开了在省电模式期间保存，验证和校正DRAM装置中的数据的方法，装置和系统。 在省电模式下，可以使用自刷新操作刷新DRAM装置中的存储单元。 该自刷新操作可能允许在DRAM器件中发生位错误。 然而，通过采用纠错编码（ECC），本发明的实施例可以检测和校正在省电模式下可能发生的这些潜在错误。 此外，在省电模式期间发生的周期性自刷新过程中，采用部分ECC校验周期来检查和校正存储器单元的子集。

公开(公告)号：US08017039B2

公开(公告)日：2011-09-13

申请号：US12933359

申请日：2009-03-18

申请人： Kenji Toda ,  Kazuyoshi Uematsu ,  Mineo Sato ,  Tetsu Umeda ,  Yutaka Ito

发明人： Kenji Toda ,  Kazuyoshi Uematsu ,  Mineo Sato ,  Tetsu Umeda ,  Yutaka Ito

IPC分类号： C09K11/08 ,  C09K11/70

CPC分类号： C09K11/7738 ,  H01J61/44 ,  H01L33/502

摘要： Provided is a fluorescent body for use in a near-ultraviolet excitation light-emitting element, comprising the compound given by formula (1), having part of element M1 and/or M2 therein replaced by an activation element (M3). M1aM2bPcO15(1) (Here, M1 represents one or more elements chosen from the group comprising Ca, Sr, and Ba; M2 represents one or more elements chosen from the group comprising Mg and Zn; a is a number between 1.5 and 2.5, inclusive; b is a number between 2.5 and 3.5, inclusive; and c is a number between 3.5 and 4.5, inclusive.) A fluorescent body in which M1 is Sr and M2 is Mg, and a fluorescent body in which M3 is Eu are preferable. Also provided are a fluorescent paste having the fluorescent body, and a near-ultraviolet excitation light-emitting element having the fluorescent body and having a high luminescent intensity.

摘要翻译： 提供一种用于近紫外激发发光元件的荧光体，其包含由式（1）给出的化合物，其中元素M1和/或M2的一部分由激活元件（M3）代替。 M1aM2bPcO15（1）（这里，M1表示选自Ca，Sr和Ba的一种或多种元素; M2表示选自Mg和Zn的一种或多种元素; a是介于1.5和2.5之间的数，包括 b是2.5和3.5之间的数字，包括端值在内; c是3.5和4.5之间的数字，包括端值。）M1是Sr和M2是Mg的荧光体和M3是Eu的荧光体是优选的。 还提供了具有荧光体的荧光膏和具有荧光体并且具有高发光强度的近紫外激发发光元件。

公开(公告)号：US20110148469A1

公开(公告)日：2011-06-23

申请号：US12641520

申请日：2009-12-18

申请人： Yutaka Ito ,  Keiichiro Abe

发明人： Yutaka Ito ,  Keiichiro Abe

IPC分类号： H03K5/153 ,  H05K7/00

CPC分类号： G11C5/04 ,  G11C7/20 ,  H01L25/0657 ,  H01L2225/06541 ,  H01L2924/0002 ,  H03K5/153 ,  H01L2924/00

摘要： Various embodiments include apparatus and methods having circuitry to detect and/or assign identification information to dice arranged in a stack and coupled by conductive paths.

摘要翻译： 各种实施例包括具有电路的装置和方法，用于检测和/或分配标识信息到布置在堆叠中并由导电路径耦合的裸片。

公开(公告)号：US07940569B2

公开(公告)日：2011-05-10

申请号：US12698808

申请日：2010-02-02

申请人： Yutaka Ito ,  Adrian J. Drexler ,  Brandi M. Jones

发明人： Yutaka Ito ,  Adrian J. Drexler ,  Brandi M. Jones

IPC分类号： G11C11/34

CPC分类号： G11C11/4074 ,  G11C5/14 ,  G11C5/144 ,  G11C7/20 ,  G11C11/4072

摘要： Apparatus, methods, and systems are disclosed, including those that are to prevent a bias voltage from rising to a higher level than a storage node voltage as the bias voltage transitions to a ground level. For example a first voltage generator may be utilized to generate a bias voltage to bias a transistor in a memory cell in a memory array. A second voltage generator may be utilized to generate an plate voltage. The memory cell may include a transistor on a substrate and a capacitor. The capacitor connects from a drain of the transistor to the plate voltage. The storage node voltage is located at the drain of the transistor. A power controller may provide an off signal to the first and second voltage generators. The bias voltage may then transition to ground from a voltage less than zero volts. The rate of the bias voltage rise to ground is such that the bias voltage is maintained at less than or equal to the storage node voltage during the transition time period.

摘要翻译： 公开了装置，方法和系统，包括当偏置电压转变到地电位时，防止偏置电压升高到高于存储节点电压的电平的装置，方法和系统。 例如，可以使用第一电压发生器来产生偏置电压以偏置存储器阵列中的存储器单元中的晶体管。 可以利用第二电压发生器来产生板电压。 存储单元可以包括衬底上的晶体管和电容器。 电容器从晶体管的漏极连接到板电压。 存储节点电压位于晶体管的漏极处。 功率控制器可以向第一和第二电压发生器提供关闭信号。 偏压可以从小于零伏的电压转变到地。 偏置电压上升到接地的速率使得偏置电压保持在小于或等于转换时间段内的存储节点电压。

公开(公告)号：US20110025194A1

公开(公告)日：2011-02-03

申请号：US12933382

申请日：2009-03-18

申请人： Kenji Toda ,  Kazuyoshi Uematsu ,  Mineo Sato ,  Tetsu Umeda ,  Yutaka Ito

发明人： Kenji Toda ,  Kazuyoshi Uematsu ,  Mineo Sato ,  Tetsu Umeda ,  Yutaka Ito

IPC分类号： C09K11/66 ,  H01J1/62 ,  C09K11/54 ,  C09K11/59

CPC分类号： C09K11/7734 ,  H01J61/44

摘要： Provided are phosphors that can exhibit higher emission luminance. Phosphors in which the activator is included in a compound represented by Formula xM1O.M2O.yM3O2 (wherein M1 represents one or more of a group comprising Ca, Sr and Ba, M2 represents Mg and/or Zn, M3 represents Si and/or Ge, x is a value in the range 4 to 6 and y is a value in the range 2 to 4). Phosphors represented by Formula M15(1−z)EuzM2M33O12 (wherein M1, M2 and M3 have the same meanings as above, and z is a value in the range 0.0001 to 0.3). The above phosphors have the same crystal structure as bredigite.

摘要翻译： 提供可以表现出更高发光亮度的荧光体。 其中活化剂包括在由式xM1O.M2O.yM3O2表示的化合物中的荧光体（其中M1表示包含Ca，Sr和Ba的一种或多种，​​M2表示Mg和/或Zn，M3表示Si和/或Ge ，x是4〜6的范围内的值，y是2〜4的范围的值）。 由式M15（1-z）表示的荧光体EuzM2M33O12（其中M1，M2和M3具有与上述相同的含义，z是0.0001至0.3的范围内的值）。 上述荧光体具有与白云石相同的晶体结构。

公开(公告)号：US07737978B2

公开(公告)日：2010-06-15

申请号：US11587483

申请日：2005-04-27

申请人： Daizaburo Nakamura ,  Yutaka Ito ,  Takeshi Okubo

发明人： Daizaburo Nakamura ,  Yutaka Ito ,  Takeshi Okubo

IPC分类号： G06T15/70

CPC分类号： A63F13/577 ,  A63F13/10 ,  A63F13/5258 ,  A63F13/537 ,  A63F13/803 ,  A63F2300/63 ,  A63F2300/64 ,  A63F2300/643 ,  A63F2300/6692 ,  G06T19/00 ,  G06T2210/21 ,  Y10S345/958

摘要： To provide a display, etc. suitable for appropriately processing display in a case where it is expected, in three-dimensional graphics display, that a viewpoint will collide with an object, a storage unit (202) of a display (201) stores the coordinates of a viewpoint and an object in a virtual three-dimensional space, moving velocities, etc., an associating unit (203) associates a real time and a virtual time in the virtual three-dimensional space, a moving unit (204) calculates the coordinates of the viewpoint and object and moving velocities, etc. at the associated virtual time to update the values stored in the storage unit (202), a display unit (205) displays the state of the virtual three-dimensional space as observed from the viewpoint, and a determination unit (206) determines whether or not the viewpoint will collide with the object after a predetermined virtual threshold period elapses, and makes the elapse of the virtual time slower than the real time in a case where it is determined that a collision will occur.

摘要翻译： 为了提供适于在预期的情况下适当地处理显示的显示器，在三维图形显示中，视点将与对象相冲突，显示器（201）的存储单元（202）存储 关联单元（203）将虚拟三维空间中的实时和虚拟时间相关联，移动单元（204）计算虚拟三维空间中的视点和对象的坐标，移动速度等，移动单元 在相关联的虚拟时间处的视点和对象的坐标以及移动速度等，以更新存储单元（202）中存储的值，显示单元（205）显示虚拟三维空间的状态，如 视点和确定单元（206）确定在经过预定的虚拟阈值周期之后视点将与对象发生冲突，并且在其为de的情况下使虚拟时间的经过慢于实时时间 终止将发生碰撞。

公开(公告)号：US20090297868A1

公开(公告)日：2009-12-03

申请号：US12127605

申请日：2008-05-27

申请人： Yutaka Ito ,  Zhenan Bao ,  Jason Locklin

发明人： Yutaka Ito ,  Zhenan Bao ,  Jason Locklin

IPC分类号： B05D3/12 ,  B05D3/02 ,  B32B9/04

CPC分类号： H01L51/0533 ,  H01L51/0545 ,  Y10T428/31663

摘要： A method for forming a self-organized monomolecular film, including at least: dissolving an alkylsilane compound having at least an alkoxysilane group or a chlorosilane group at one end of a molecule in an organic solvent having a dielectric constant of 3.0 or more to 6.0 or less to obtain a solution; subsequently coating the solution on a base material or immersing the base material into the solution; and subsequently drying the solution located on the base material.

摘要翻译： 一种形成自组织单分子膜的方法，至少包括：将分子一端具有至少烷氧基硅烷基或氯硅烷基的烷基硅烷化合物溶解在介电常数为3.0以上至6.0的有机溶剂中，或 较少获得解决方案; 随后将溶液涂覆在基材上或将基材浸入溶液中; 随后干燥位于基材上的溶液。

公开(公告)号：US20090193301A1

公开(公告)日：2009-07-30

申请号：US12318840

申请日：2009-01-09

申请人： Yutaka Ito ,  Takeshi Hashimoto

发明人： Yutaka Ito ,  Takeshi Hashimoto

IPC分类号： H03M13/05 ,  G06F11/00 ,  G06F11/07

CPC分类号： G11C11/406 ,  G11C2211/4061 ,  G11C2211/4062

摘要： Disclosed is a memory device including an error rate measurement circuit and a control circuit. The error rate measurement circuit, carrying a BIST circuit, reads out and writes data for an area for monitor bits every refresh period to detect an error rate (error count) with the refresh period. The control circuit performs control for elongating and shortening the refresh period so that a desired error rate will be achieved. The BIST circuit issues an internal command and an internal address and drives the DRAM from inside. The BIST circuit writes and reads out desired data, compares the monitor bits to expected values (error decision) and counts the errors.

摘要翻译： 公开了一种包括错误率测量电路和控制电路的存储器件。 携带BIST电路的误差率测量电路每刷新周期读出并写入用于监视位的区域的数据，以检测刷新周期的错误率（错误计数）。 控制电路进行用于延长和缩短刷新周期的控制，从而实现期望的误码率。 BIST电路发出内部命令和内部地址，并从内部驱动DRAM。 BIST电路写入和读出所需的数据，将监视位与预期值进行比较（错误判定），并对错误进行计数。