Abstract:
A method for extracting path overhead (POH) data blocks from a data stream in a 64B/66B-block communication link, the method includes receiving at a sink node a data stream in a 64B/66B-block communication link, detecting within the data stream at a PCS sublayer a micro-packet starting with an /S/ control block, including K POH data blocks, and ending with a /T/ control block, extracting the micro-packet from the data stream, and extracting the POH data blocks from the micro-packet.
Abstract:
A method and apparatus for decoding are disclosed. The method includes receiving a first Forward Error Correction (FEC) block of read values, starting a hard-decode process in which a number of check node failures is identified and, during the hard-decode process comparing the identified number of check node failures to a decode threshold. When the identified number of check node failures is not greater than the decode threshold the hard-decode process is continued. When the identified number of check node failures is greater than the decode threshold, the method includes: stopping the hard-decode process prior to completion of the hard-decode process; generating output indicating that additional reads are required; receiving one or more additional FEC blocks of read values, mapping the first FEC block of read values and the additional FEC blocks of read values into soft-input values; and performing a soft-decode process on the soft-input values.
Abstract:
A method for programming a resistive random-access memory (ReRAM) cell includes passing a first current through the ReRAM device for a first period of time, the first current selected to create a leakage path through the ReRAM device, and after passing the first current through the ReRAM device passing a second current through the ReRAM device for a second period of time shorter than the first period of time, the second current selected to create a current path having a desired resistance through the leakage path through the ReRAM device.
Abstract:
A method for extracting POH data blocks and a MOS control block from a data stream in a 64B/66B-block communication link including receiving a data stream, finding a first combination of a MOS control block and K POH data blocks including CRC data in the data stream, extracting the MOS control block and the K POH data blocks from the data stream, searching in a window for a subsequent combination of a MOS control block and K POH data blocks and removing them if at least one of them are found, if neither the subsequent MOS control block nor the K POH data blocks are found within the predetermined window, extracting from the data stream K+1 64B/66B-blocks in the predetermined window.
Abstract:
An integrated circuit includes a plurality of logic function circuits disposed on the integrated circuit and interconnected by metal interconnect lines to form a logic network. A plurality of configurable logic function circuits is also disposed on the integrated circuit, each configurable logic function circuit being disposed on a respective area on the integrated circuit and not interconnected by the metal interconnect lines to form the logic network.
Abstract:
The invention relates to methods for supplying current to an auxiliary power supply for the control circuit of a switching regulator. The auxiliary power supply is connected in parallel to a first switch of the switching regulator. The auxiliary power supply comprises a second switch. During the nonswitching stage of the switching regulator, the second switch has significant impedance so as to power up the auxiliary power supply gradually and to suppress the flow of large or oscillatory currents which may cause damage or create interference. During the switching stage of the switching regulator, the second switch has negligible impedance so as to avoid undue dissipation within the path for the supply of current.
Abstract:
A switching linear amplifier has a DC-DC converter to increase a low input DC voltage to a first high voltage DC. A high voltage high frequency inverter is coupled to the DC-DC converter to generate high voltage pulses. A multistage voltage multiplier is coupled to the high voltage high frequency inverter to generate a second high voltage DC. A controlled charge and discharge circuit is coupled to the multistage voltage multiplier to drive a capacitive load.
Abstract:
The invention provides a novel method of transmit beamforming, which allows compact analog implementation of complex digital algorithms without compromising their features. It is aimed to support envelope shaping, apodization, and phase rotation per channel and per firing. Each of three embodiments represents a complete transmit channel driven by pulse-width modulated (PWM) waveforms stored in a conventional sequence memory. PWM signals controls the transmit pulse envelope (shape) by changing the duty cycle of the carrier. Beamformation data are loaded prior to a firing via serial interface. Under the direction of a controller, the circuitry allows high precision (beyond sampling rate) phase rotation of the carrier. It also provides transmit apodization (aperture weighting), which maintains an optimal trade-off among low sidelobe level and widening of the mainlobe. Implementing such an IC, the manufacturing cost of a high-end ultrasound system can be reduced. Equally, the proposed solution makes the benefits of digital transmit beamformers available to midrange and entry-level machines since it merely requires a modified programming of the sequence memory.
Abstract:
A ballast circuit for a Light Emitting Diode (LED) has a regulator element coupled to the LED and to an input voltage source. A control circuit is coupled to the LED and to an input voltage source. A first switching device is coupled in series with the regulator element. A second switching device is coupled to the input voltage and the control circuit.
Abstract:
A battery cover assembly having integrated battery condition monitoring for measuring electrical current passing to and from a battery post, including an electrically conductive collar for connecting to a post of a battery, and an electrically conductive terminal for receiving a connector of a load. An electrically conductive resistor having a known resistance extends between outer surfaces of the collar and the terminal. The battery cover assembly is incorporated into a battery, which may also include a voltage measuring device connected between the outer surfaces of the collar and the terminal for measuring the voltage drop across the resistor, memory for storing the known resistance of the resistor, and a digital processor programmed to receive the measured voltage drop from the voltage measuring device, retrieve the known resistance from the memory, and calculate current flow through the resistor based on the measured voltage drop and the known resistance, whereby current flow to and from the battery can be measured. A temperature measuring device may also be incorporated to measure temperature of the resistor located between the outer surfaces of the collar and the terminal. A resistance-temperature table may be stored in the memory and used to calculate the actual resistance of the resistor and then to compensate the current value from the voltage measured across the resistor.