公开(公告)号：US20120182048A1

公开(公告)日：2012-07-19

申请号：US13345308

申请日：2012-01-06

申请人： Paul Eaton

发明人： Paul Eaton

IPC分类号： H03K19/20

CPC分类号： H03K19/007 ,  H03K19/00338

摘要： This invention relates to Multiple Interlocked Cells (MICE) design as a hardening technique for CMOS logic gates consisting of two or more redundant nodes with node isolation components. This technique is used to modify existing standard CMOS logic gates or create new complex logic gates using common mask layers existing at ultra-deep sub-micron CMOS foundries. For single node upset immunity in logic or register, a primary cell and a redundant cell are used. For multi-node immunity, the primary cell is combined with two or more redundant nodes are used with physical layout spacing techniques which will insure that a single particle track cannot upset all three nodes simultaneously, and logic circuits built using this technique are immune to upsets in any environment. Circuits built using the MICE technique are also immune to single event transients without requiring the large time delays used in other hardening techniques.

摘要翻译： 本发明涉及作为由具有节点隔离组件的两个或多个冗余节点组成的CMOS逻辑门的硬化技术的多重联锁单元（MICE）设计。 该技术用于修改现有的标准CMOS逻辑门，或者使用在超深亚微米CMOS晶圆代工厂中存在的常用掩模层来创建新的复杂逻辑门。 对于逻辑或寄存器中的单节点不稳定性，使用主单元和冗余单元。 对于多节点免疫，主单元与两个或多个冗余节点组合使用物理布局间隔技术，这将确保单个粒子轨道不会同时打乱所有三个节点，并且使用此技术构建的逻辑电路免受烦扰 在任何环境中。 使用MICE技术构建的电路也不受单事件瞬变的影响，无需在其他硬化技术中使用较大的时间延迟。

公开(公告)号：US08014184B1

公开(公告)日：2011-09-06

申请号：US12558770

申请日：2009-09-14

申请人： Austin H. Lesea

发明人： Austin H. Lesea

IPC分类号： G11C5/06

CPC分类号： H03K19/00338 ,  G11C11/412

摘要： A memory cell has a data value storage circuit and a data address circuit that includes a first address transistor formed in a first address transistor well and a second address transistor formed in a second address transistor well. The first address transistor is coupled between a data node and the second address transistor, and the second address transistor is coupled between the first address transistor and the data value storage circuit. The first address transistor well is coupled to an intermediate node between the first address transistor and the second address transistor, and the second address transistor well is coupled to a ground terminal.

摘要翻译： 存储单元具有数据值存储电路和数据地址电路，其包括形成在第一地址晶体管阱中的第一地址晶体管和形成在第二地址晶体管阱中的第二地址晶体管。 第一地址晶体管耦合在数据节点和第二地址晶体管之间，第二地址晶体管耦合在第一地址晶体管和数据值存储电路之间。 第一地址晶体管阱耦合到第一地址晶体管和第二地址晶体管之间的中间节点，并且第二地址晶体管阱耦合到接地端子。

公开(公告)号：US07852107B1

公开(公告)日：2010-12-14

申请号：US12707935

申请日：2010-02-18

申请人： Prasanna Sundararajan

发明人： Prasanna Sundararajan

IPC分类号： H03K19/003 ,  H03K19/007 ,  G01R31/28

CPC分类号： H03K19/00338 ,  H03K19/0075 ,  H03K19/17764

摘要： In one embodiment of the invention, a method is provided for protecting against single event upsets of a circuit in programmable logic. Configuration memory cells of the programmable logic are configured to implement first and second copies of the circuit. In response to detecting a single event upset of one of the configuration memory cells, an address of the one of the configuration memory cells is determined. The one of the first and second copies of the circuit in which the single event upset occurred is determined from the address of the one of the configuration memory cells. The output from the one of the first and second copies of the circuit in which the single event upset did not occur is selected as an output of the circuit.

摘要翻译： 在本发明的一个实施例中，提供了一种用于防止在可编程逻辑中的电路的单个事件的不匹配的方法。 可编程逻辑的配置存储单元被配置为实现电路的第一和第二副本。 响应于检测到一个配置存储器单元的单个事件不正常，确定配置存储器单元之一的地址。 发生单次事件不适的电路的第一和第二副本之一由配置存储器单元之一的地址确定。 选择其中不发生单事件不正常的电路的第一和第二副本之一的输出作为电路的输出。

公开(公告)号：US20100264953A1

公开(公告)日：2010-10-21

申请号：US12763139

申请日：2010-04-19

申请人： Klas Olof Lilja

发明人： Klas Olof Lilja

IPC分类号： H03K19/003 ,  G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/12 ,  H01L27/0207 ,  H01L27/11807 ,  H03K19/00338 ,  Y02P90/265

摘要： This invention comprises a layout method to effectively protect electronic circuits against soft errors (non-destructive errors) and circuit cells, which are protected against soft errors. The invention applies a layout method to sequential and combinational logic to generate specific circuit cells with netlists and layouts which are hardened against single event generated soft-errors. It also devices methods of how two or more such cells should be laid out and placed relative to each other, in order to have the best global soft-error protection.

摘要翻译： 本发明包括一种有效保护电子电路免受软错误（非破坏性错误）和电路单元的布局方法，该电路可防止软错误。 本发明对顺序和组合逻辑应用布局方法，以生成具有针对单个事件产生的软错误来加固的网表和布局的特定电路单元。 它还设置了如何将两个或更多个这样的单元相对于彼此布置和放置的方法，以便具有最佳的全局软错误保护。

公开(公告)号：US20100207658A1

公开(公告)日：2010-08-19

申请号：US12768045

申请日：2010-04-27

申请人： Rajit Manohar ,  Clinton W. Kelly

发明人： Rajit Manohar ,  Clinton W. Kelly

IPC分类号： H03K19/003 ,  H01R43/00

CPC分类号： H03K19/007 ,  H03K19/00338 ,  Y10T29/49002 ,  Y10T29/49117

摘要： New and improved methods and circuit designs for asynchronous circuits that are tolerant to transient faults, for example of the type introduced through radiation or, more broadly, single-event effects. SEE-tolerant configurations are shown and described for combinational logic circuits, state-holding logic circuits and SRAM memory circuits.

摘要翻译： 用于异步电路的新的和改进的方法和电路设计，其容忍瞬态故障，例如通过辐射引入的类型，或更广泛地，单事件效应。 显示和描述了组合逻辑电路，状态保持逻辑电路和SRAM存储器电路的SEE容限配置。

公开(公告)号：US20100176841A1

公开(公告)日：2010-07-15

申请号：US12684010

申请日：2010-01-07

申请人： Wonjin Jang ,  Christopher D. Moore ,  Alain J. Martin

发明人： Wonjin Jang ,  Christopher D. Moore ,  Alain J. Martin

IPC分类号： H03K19/003

CPC分类号： H03K19/00338

摘要： Single Event Upset (SEU, also referred to as soft error) tolerant arbiters, bare arbiters, and filters are disclosed. An arbiter provides a filter section, and a bare arbiter, coupled to the filter section. The bare arbiter includes a redundant first input and a redundant second input, and a redundant first output and a redundant second output. A pull-down transistor in the bare arbiter conditionally overpowers a corresponding pull-up transistor in the bare arbiter when a contention condition is present in the bare arbiter.

摘要翻译： 公开了单事件颠覆（SEU，也称为软错误）容忍仲裁器，裸机仲裁器和过滤器。 仲裁器提供耦合到滤波器部分的滤波器部分和裸仲裁器。 裸仲裁器包括冗余第一输入和冗余第二输入，冗余第一输出和冗余第二输出。 当仲裁器中存在竞争条件时，裸仲裁器中的下拉晶体管有条件地超过裸仲裁器中的相应上拉晶体管。

公开(公告)号：US07719304B1

公开(公告)日：2010-05-18

申请号：US12117320

申请日：2008-05-08

申请人： Lawrence T. Clark ,  Jonathan E. Knudsen

发明人： Lawrence T. Clark ,  Jonathan E. Knudsen

IPC分类号： H03K19/007

CPC分类号： H03K3/0375 ,  H03K3/0372 ,  H03K19/00338

摘要： The present invention provides a radiation hardened flip-flop formed from a modified temporal latch and a modified dual interlocked storage cell (DICE) latch. The temporal latch is configured as the master latch and provides four output storage nodes, which represent outputs of the temporal latch. The DICE latch is configured as the slave latch and is made of two cross-coupled inverter latches, which together provide four DICE storage nodes. The four outputs of the temporal latch are used to write the four DICE storage nodes of the DICE latch. The temporal latch includes at least one feedback path that includes a delay element, which provides a delay.

摘要翻译： 本发明提供一种由修改的时间锁存器和修改的双重互锁存储单元（DICE）锁存器形成的辐射硬化触发器。 时间锁存器被配置为主锁存器并且提供四个输出存储节点，其表示时间锁存器的输出。 DICE锁存器配置为从锁存器，由两个交叉耦合的反相器锁存器组成，它们共同提供四个DICE存储节点。 时间锁存器的四个输出用于写入DICE锁存器的四个DICE存储节点。 时间锁存器包括至少一个反馈路径，其包括提供延迟的延迟元件。

公开(公告)号：US20100079183A1

公开(公告)日：2010-04-01

申请号：US12286286

申请日：2008-09-30

申请人： David C. Lawson ,  Michael A. Belzecky

发明人： David C. Lawson ,  Michael A. Belzecky

IPC分类号： H03K3/037

CPC分类号： H03K3/0375 ,  H03K3/356113 ,  H03K3/356182 ,  H03K19/00338 ,  H03K19/00392

摘要： Tri-stating transistors which are controlled by the latch enable lines isolate holding transistors from the latch node during setting of the latch. The tri-stating transistors are connected to the holding transistors and the latch node which allows the node to float and assume a third state during setting of the latch when the latch is enabled.

摘要翻译： 由锁存器使能线控制的三态晶体管在锁存器的置位期间将保持晶体管与锁存器节点隔离。 三态晶体管连接到保持晶体管和锁存节点，当锁存器被使能时，锁存节点允许节点浮动并且在锁存器的设置期间呈现第三状态。

公开(公告)号：US20090230988A1

公开(公告)日：2009-09-17

申请号：US11720213

申请日：2005-11-28

申请人： Andre Krijn Nieuwland ,  Theodorus Gerardus Albertus Heijmen

发明人： Andre Krijn Nieuwland ,  Theodorus Gerardus Albertus Heijmen

IPC分类号： H03K19/007 ,  G06F17/50

CPC分类号： H03K19/00338 ,  H03K19/00392

摘要： An electronic device with logic circuitry (LC) is provided. The logic circuitry (LC) comprises at least one electronic unit (EU), in particular one logic gate with a first electronic component (EC1) for performing logic operations; and at least one second electronic component (EC2) for improving the soft-error sensitivity of the logic circuitry (LC). The first and the second electronic component (EC1, EC2) are implemented with substantially the same logical function. The second electronic component (EC2) is redundant. In addition, the inputs of the first and the second electronic component (EC1, E2) are coupled and the outputs of the first and the second electronic component (EC1, E2) are coupled, respectively.

摘要翻译： 提供具有逻辑电路（LC）的电子设备。 逻辑电路（LC）包括至少一个电子单元（EU），特别是具有用于执行逻辑操作的第一电子部件（EC1）的一个逻辑门; 以及用于改善逻辑电路（LC）的软错误灵敏度的至少一个第二电子部件（EC2）。 第一和第二电子部件（EC1，EC2）以基本上相同的逻辑功能实现。 第二电子元件（EC2）是多余的。 另外，第一和第二电子部件（EC1，E2）的输入被耦合，并且第一和第二电子部件（EC1，E2）的输出分别耦合。

公开(公告)号：US07565590B2

公开(公告)日：2009-07-21

申请号：US11820714

申请日：2007-06-19

申请人： Michael Nicolaidis

发明人： Michael Nicolaidis

IPC分类号： G01R31/317 ,  G01R31/40

CPC分类号： G06F11/1497 ,  G06F11/10 ,  H03K19/00338

摘要： The invention concerns a circuit protected against transitory perturbations, comprising a combinatorial logic circuit (10), having at least an output (A); a circuit (20) generating an error control code for said output, and a storage element (24) provided at said output, controlled by the circuit generating a control code to be transparent when the control code is correct, and to maintain its status when the control code is incorrect.

摘要翻译： 本发明涉及一种防止瞬时扰动的电路，包括具有至少一个输出（A）的组合逻辑电路（10）; 产生用于所述输出的错误控制代码的电路（20）和设置在所述输出端的存储元件（24），所述存储元件（24）由所述电路控制，所述电路在所述控制代码正确时产生要透明的控制代码，并且当 控制代码不正确。