公开(公告)号：US11374567B2

公开(公告)日：2022-06-28

申请号：US15430484

申请日：2017-02-11

申请人： Klas Olof Lilja

发明人： Klas Olof Lilja

IPC分类号： H03K19/00 ,  H03K3/03 ,  G11C11/41 ,  H03K3/037 ,  G11C11/412 ,  H03K23/00 ,  H03K3/012 ,  H03K19/003 ,  G11C11/413 ,  G11C11/419

摘要： This invention comprises a new way to connect a control, CK, and data, D, signal into a basic cross-coupled INV pair, and into certain other basic sequential logic circuits, to control the writing in of a new data value, D, into the sequential logic circuit cell. The invention concerns logic circuit in complementary metal-oxide-semiconductor (CMOS) technology. It connects additional p-type and n-type MOSFET devices in a novel manner to accomplish the desired control functions.

公开(公告)号：US20160048624A1

公开(公告)日：2016-02-18

申请号：US14666043

申请日：2015-03-23

申请人： Klas Olof Lilja

发明人： Klas Olof Lilja

IPC分类号： G06F17/50 ,  H01L27/02

CPC分类号： G06F17/5072 ,  G06F17/5068 ,  G06F17/5081 ,  G06F2217/12 ,  H01L27/0207 ,  H03K19/0033 ,  H03K19/00338 ,  H03K19/20 ,  Y02P90/265

摘要： In various embodiments, an integrated circuit derived from an integrated circuit layout is disclosed. In some embodiments, the integrated circuit layout comprises a first contact area from a first logic cell and a second contact area from a second logic cell. The second contact area comprises a non-zero, non-opposing effect with respect to the first contact area. The first contact area and the second contact area comprise a first distance. When the first distance is below a predetermined threshold, the first logic cell and the second logic cell are placed along a first R-line of the circuit and a third contact area comprising an opposing effect with respect to the first contact area and the second contact area is placed between the first contact area and second contact area.

摘要翻译： 在各种实施例中，公开了从集成电路布局导出的集成电路。 在一些实施例中，集成电路布局包括来自第一逻辑单元的第一接触区域和来自第二逻辑单元的第二接触区域。 第二接触区域包括相对于第一接触区域的非零非相反效应。 第一接触区域和第二接触区域包括第一距离。 当第一距离低于预定阈值时，第一逻辑单元和第二逻辑单元沿电路的第一R线放置，并且第三接触区包括相对于第一接触区和第二接触的相反作用 区域被放置在第一接触区域和第二接触区域之间。

公开(公告)号：US09081926B2

公开(公告)日：2015-07-14

申请号：US14026648

申请日：2013-09-13

申请人： Klas Olof Lilja

发明人： Klas Olof Lilja

IPC分类号： G06F17/50 ,  H03K19/003 ,  H03K19/20

CPC分类号： G06F17/5022 ,  G06F17/5068 ,  G06F2217/12 ,  H03K19/0033 ,  H03K19/00338 ,  H03K19/20 ,  Y02P90/265

摘要： This invention comprises a layout method to effectively protect logic circuits against soft errors (non-destructive errors) and circuit cells, with layout, which are protected against soft errors. In particular, the method protects against cases where multiple nodes in circuit are affected by a single event. These events lead to multiple errors in the circuit, and while several methods exist to deal with single node errors, multiple node errors are very hard to deal with using any currently existing protection methods. The method is particularly useful for CMOS based logic circuits in modem technologies (.ltoreq.90 nm), where the occurrence of multiple node pulses becomes high (due to the high integration level). It uses a unique layout configuration, which makes the circuits protected against single event generated soft-errors.

摘要翻译： 本发明包括一种有效保护逻辑电路免受软错误（非破坏性错误）和电路单元的布局方法，其布局具有防止软错误的布局。 特别地，该方法防止电路中的多个节点受单个事件影响的情况。 这些事件导致电路中的多个错误，并且虽然存在用于处理单节点错误的几种方法，但是多个节点错误很难处理使用任何当前存在的保护方法。 该方法对于调制解调器技术（.ltoreq.90nm）中的基于CMOS的逻辑电路特别有用，其中多个节点脉冲的发生变高（由于高集成度）。 它使用独特的布局配置，这使得电路可以防止单个事件产生的软错误。

公开(公告)号：US08566770B2

公开(公告)日：2013-10-22

申请号：US13277135

申请日：2011-10-19

申请人： Klas Olof Lilja

发明人： Klas Olof Lilja

IPC分类号： G06F17/50 ,  H03K19/003 ,  H03K19/007

CPC分类号： G06F17/5022 ,  G06F17/5068 ,  G06F2217/12 ,  H03K19/0033 ,  H03K19/00338 ,  H03K19/20 ,  Y02P90/265

摘要： This invention comprises a layout method to effectively protect logic circuits against soft errors (non-destructive errors) and circuit cells, with layout, which are protected against soft errors. In particular, the method protects against cases where multiple nodes in circuit are affected by a single event. These events lead to multiple errors in the circuit, and while several methods exist to deal with single node errors, multiple node errors are very hard to deal with using any currently existing protection methods. The method is particularly useful for CMOS based logic circuits in modern technologies (.ltoreq.90 nm), where the occurrence of multiple node pulses becomes high (due to the high integration level). It uses a unique layout configuration, which makes the circuits protected against single event generated soft-errors.

摘要翻译： 本发明包括一种有效保护逻辑电路免受软错误（非破坏性错误）和电路单元的布局方法，其布局具有防止软错误的布局。 特别地，该方法防止电路中的多个节点受单个事件影响的情况。 这些事件导致电路中的多个错误，并且虽然存在用于处理单节点错误的几种方法，但是多个节点错误很难处理使用任何当前存在的保护方法。 该方法对于现代技术（.ltoreq.90nm）中的基于CMOS的逻辑电路特别有用，其中多个节点脉冲的发生变高（由于高集成度）。 它使用独特的布局配置，这使得电路可以防止单个事件产生的软错误。

公开(公告)号：US20100264953A1

公开(公告)日：2010-10-21

申请号：US12763139

申请日：2010-04-19

申请人： Klas Olof Lilja

发明人： Klas Olof Lilja

IPC分类号： H03K19/003 ,  G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/12 ,  H01L27/0207 ,  H01L27/11807 ,  H03K19/00338 ,  Y02P90/265

摘要： This invention comprises a layout method to effectively protect electronic circuits against soft errors (non-destructive errors) and circuit cells, which are protected against soft errors. The invention applies a layout method to sequential and combinational logic to generate specific circuit cells with netlists and layouts which are hardened against single event generated soft-errors. It also devices methods of how two or more such cells should be laid out and placed relative to each other, in order to have the best global soft-error protection.

摘要翻译： 本发明包括一种有效保护电子电路免受软错误（非破坏性错误）和电路单元的布局方法，该电路可防止软错误。 本发明对顺序和组合逻辑应用布局方法，以生成具有针对单个事件产生的软错误来加固的网表和布局的特定电路单元。 它还设置了如何将两个或更多个这样的单元相对于彼此布置和放置的方法，以便具有最佳的全局软错误保护。

公开(公告)号：US11683040B1

公开(公告)日：2023-06-20

申请号：US17803280

申请日：2022-04-18

申请人： Klas Olof Lilja

发明人： Klas Olof Lilja

IPC分类号： H03K19/1776 ,  H03K19/17736 ,  H03K19/17784 ,  H03K19/23 ,  G06F30/392 ,  G06F30/398

CPC分类号： H03K19/1776 ,  G06F30/392 ,  G06F30/398 ,  H03K19/17744 ,  H03K19/17784 ,  H03K19/23

摘要： This invention comprises an integrated circuit in CMOS technology which can act as a regular sequential logic latch, having one data signal input, or as a voting latch, having three data signal inputs. The circuit schematic of this integrated circuit is such that it allows for a certain placement of the devices in the physical, manufactured integrated circuit that makes it possible to optimize the arrangement of the n-type MOSFET devices and p-type MOSFET devices in the circuit independently, using the Layout Optimization through Error Aware Positioning (LEAP), and thereby to remove, or reduce, the occurrence of radiation generated soft errors.

公开(公告)号：US08468484B2

公开(公告)日：2013-06-18

申请号：US13425231

申请日：2012-03-20

申请人： Klas Olof Lilja

发明人： Klas Olof Lilja

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

摘要： This invention comprises a layout method to effectively protect logic circuits against soft errors (non-destructive errors) and circuit cells, with layout, which are protected against soft errors. In particular, the method protects against cases where multiple nodes in circuit are affected by a single event. These events lead to multiple errors in the circuit, and while several methods exist to deal with single node errors, multiple node errors are very hard to deal with using any currently existing protection methods. The method is particularly useful for CMOS based logic circuits in modem technologies (.ltoreq.90 nm), where the occurrence of multiple node pulses becomes high (due to the high integration level). It uses a unique layout configuration, which makes the circuits protected against single event generated soft-errors.

摘要翻译： 本发明包括一种有效保护逻辑电路免受软错误（非破坏性错误）和电路单元的布局方法，其布局具有防止软错误的布局。 特别地，该方法防止电路中的多个节点受单个事件影响的情况。 这些事件导致电路中的多个错误，并且虽然存在用于处理单节点错误的几种方法，但是多个节点错误很难处理使用任何当前存在的保护方法。 该方法对于调制解调器技术（.ltoreq.90nm）中的基于CMOS的逻辑电路特别有用，其中多个节点脉冲的发生变高（由于高集成度）。 它使用独特的布局配置，这使得电路可以防止单个事件产生的软错误。

公开(公告)号：US20190081627A1

公开(公告)日：2019-03-14

申请号：US15430484

申请日：2017-02-11

申请人： Klas Olof Lilja

发明人： Klas Olof Lilja

IPC分类号： H03K19/00 ,  H03K3/037

摘要： This invention comprises a new way to connect a control, CK, and data, D, signal into a basic cross-coupled INV pair, and into certain other basic sequential logic circuits, to control the writing in of a new data value, D, into the sequential logic circuit cell. The invention concerns logic circuit in complementary metal-oxide-semiconductor (CMOS) technology. It connects additional p-type and n-type MOSFET devices in a novel manner to accomplish the desired control functions.

公开(公告)号：US20140157223A1

公开(公告)日：2014-06-05

申请号：US14060162

申请日：2013-10-22

申请人： Klas Olof Lilja

发明人： Klas Olof Lilja

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  G06F17/5068 ,  G06F17/5081 ,  G06F2217/12 ,  H01L27/0207 ,  H03K19/0033 ,  H03K19/00338 ,  H03K19/20 ,  Y02P90/265

摘要： In various embodiments, an integrated circuit layout is disclosed. In one embodiments, the integrated circuit layout comprises a first contact area from a first logic cell and a second contact area from a second logic cell. The second contact area comprises a non-zero, non-opposing effect with respect to the first contact area. The first contact area and the second contact area comprise a first distance. When the first distance is below a predetermined threshold the first logic cell and the second logic cell are placed along a first R-line of the circuit and a third contact area comprising an opposing effect with respect to the first contact area and the second contact area is placed between the first contact area and second contact area.

摘要翻译： 在各种实施例中，公开了集成电路布局。 在一个实施例中，集成电路布局包括来自第一逻辑单元的第一接触区域和来自第二逻辑单元的第二接触区域。 第二接触区域包括相对于第一接触区域的非零非相反效应。 第一接触区域和第二接触区域包括第一距离。 当第一距离低于预定阈值时，第一逻辑单元和第二逻辑单元沿着电路的第一R线布置，并且第三接触区域包括相对于第一接触区域和第二接触区域的相反作用 被放置在第一接触区域和第二接触区域之间。

公开(公告)号：US20130227499A1

公开(公告)日：2013-08-29

申请号：US13463706

申请日：2012-05-03

申请人： Klas Olof Lilja

发明人： Klas Olof Lilja

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F17/5068 ,  G06F2217/12 ,  H03K19/0033 ,  H03K19/00338 ,  H03K19/20 ,  Y02P90/265

摘要： This invention comprises a layout method to effectively protect logic circuits against soft errors (non-destructive errors) and circuit cells, with layout, which are protected against soft errors. In particular, the method protects against cases where multiple nodes in circuit are affected by a single event. These events lead to multiple errors in the circuit, and while several methods exist to deal with single node errors, multiple node errors are very hard to deal with using any currently existing protection methods. The method is particularly useful for CMOS based logic circuits in modem technologies (.ltoreq.90 nm), where the occurrence of multiple node pulses becomes high (due to the high integration level). It uses a unique layout configuration, which makes the circuits protected against single event generated soft-errors.

摘要翻译： 本发明包括一种有效保护逻辑电路免受软错误（非破坏性错误）和电路单元的布局方法，其布局具有防止软错误的布局。 特别地，该方法防止电路中的多个节点受单个事件影响的情况。 这些事件导致电路中的多个错误，并且虽然存在用于处理单节点错误的几种方法，但是多个节点错误很难处理使用任何当前存在的保护方法。 该方法对于调制解调器技术（.ltoreq.90nm）中的基于CMOS的逻辑电路特别有用，其中多个节点脉冲的发生变高（由于高集成度）。 它使用独特的布局配置，这使得电路可以防止单个事件产生的软错误。