公开(公告)号：US20140139269A1

公开(公告)日：2014-05-22

申请号：US13841114

申请日：2013-03-15

申请人： SK HYNIX INC.

发明人： Chun-Seok JEONG

IPC分类号： H03K3/36

CPC分类号： H03K3/36 ,  G11C5/02 ,  G11C7/1048 ,  H03K19/018585 ,  H03K19/018592

摘要： A multi-chip system may include a plurality of chips, and a channel shared by the plurality of chips. At least one of the plurality of chips includes a transmission circuit configured to transmit a signal to the channel. Drivability of the transmission circuit is adjusted based on a number of the plurality of chips.

摘要翻译： 多芯片系统可以包括多个芯片，以及由多个芯片共享的通道。 多个芯片中的至少一个包括被配置为向信道发送信号的发送电路。 基于多个芯片的数量来调整发送电路的可驱动性。

公开(公告)号：US08601254B1

公开(公告)日：2013-12-03

申请号：US12759426

申请日：2010-04-13

申请人： Harold Kutz ,  Timothy Williams ,  Bert Sullam ,  Robert W. Metzler ,  Craig Nemecek ,  Eric Blom ,  Melany Richmond ,  Warren Snyder ,  David G. Wright ,  Jeffrey Erickson ,  Greg Verge

发明人： Harold Kutz ,  Timothy Williams ,  Bert Sullam ,  Robert W. Metzler ,  Craig Nemecek ,  Eric Blom ,  Melany Richmond ,  Warren Snyder ,  David G. Wright ,  Jeffrey Erickson ,  Greg Verge

IPC分类号： G06F1/24 ,  H03K19/173

CPC分类号： G06F1/24 ,  H03K19/018585 ,  H03K19/018592 ,  H03K19/1732

摘要： A programmable system includes an input/output (I/O) pin that is configurable into multiple operational states. The programmable system further includes a memory device to store configuration data that, when provided to the I/O pin, causes the I/O pin to reconfigure into one of the operational states. When power is supplied to the system, the memory device is configured to provide the configuration data to the I/O pin prior to a system microcontroller becoming operational responsive to the power.

摘要翻译： 可编程系统包括可配置为多种工作状态的输入/输出（I / O）引脚。 可编程系统还包括存储器件，用于存储当提供给I / O引脚时使I / O引脚重新配置为其中一个操作状态的配置数据。 当向系统供电时，存储器件被配置为在系统微控制器响应于电力而变得可操作之前将配置数据提供给I / O引脚。

公开(公告)号：US20130285725A1

公开(公告)日：2013-10-31

申请号：US13930662

申请日：2013-06-28

申请人： Altera Corporation

发明人： John Henry Bui ,  Lay Hock Khoo ,  Khai Nguyen ,  Chiakang Sung ,  Ket Chiew Sia

IPC分类号： H03K5/156

CPC分类号： H03K5/1565 ,  H03K19/018592 ,  H03K19/09429

摘要： Integrated circuits with clock generation and distribution circuitry are provided. Integrated circuits may include phase-locked loops configured to generate multiple clock signals that are delayed versions of one another. The clocks signal may be distributed to various regions on an integrated circuit using serially connected clock buffer blocks. Each buffer block may include bidirectional pairs of buffer circuits coupled in parallel. Each buffer circuit may have a first input configured to receive an input clock signal, an output at which a corrected version of the input clock signal is provided (e.g., an output at which an output clock signal with desired duty cycle is provided), a second input that receives a first delayed clock signal for setting the desired duty cycle for the output clock signal, and a third input that receives a second delayed clock signal that is high at least when the first delayed clock signal rises high.

公开(公告)号：US08531228B2

公开(公告)日：2013-09-10

申请号：US13037866

申请日：2011-03-01

申请人： Andreas Johannes Köllmann ,  Steffen Rode

发明人： Andreas Johannes Köllmann ,  Steffen Rode

IPC分类号： H03L5/00

CPC分类号： H03K19/018507 ,  H03K19/018592

摘要： Level-shifting devices and methods allow signals to be passed between input/output (I/O) ports. One such device comprises a first output driver that drives a first I/O port in response to a first control signal. A second output driver drives a second I/O port in response to a second control signal. A first comparator circuit, responsive to a first reference voltage and a voltage at the first I/O port, generates the second control signal. A limiter circuit limits driving of the second I/O port, by the second driver, to a limiting voltage that responsive to a the second I/O port over a first range of signaling voltages, and constrained to a set value over a second range. A voltage reference generating circuit generates a second reference voltage. A second comparator circuit generates the first control signal in response to the second reference voltage and the second I/O port.

摘要翻译： 电平转换装置和方法允许在输入/输出（I / O）端口之间传递信号。 一个这样的设备包括响应于第一控制信号驱动第一I / O端口的第一输出驱动器。 第二输出驱动器响应于第二控制信号驱动第二I / O端口。 响应于第一参考电压和第一I / O端口处的电压的第一比较器电路产生第二控制信号。 限制器电路将第二驱动器的第二I / O端口的驱动限制为在第一信号电压范围上响应于第二I / O端口的限制电压，并且限制在第二范围上的设定值 。 电压基准产生电路产生第二参考电压。 第二比较器电路响应于第二参考电压和第二I / O端口产生第一控制信号。

公开(公告)号：US08350593B2

公开(公告)日：2013-01-08

申请号：US13015246

申请日：2011-01-27

申请人： Tomoaki Isozaki

发明人： Tomoaki Isozaki

IPC分类号： H03K19/0175 ,  H03K19/0185 ,  H03K19/094

CPC分类号： H03K19/018592 ,  H01L25/07 ,  H01L27/092 ,  H01L29/78 ,  H01L2924/0002 ,  H03K3/038 ,  H03K19/018521 ,  H01L2924/00

摘要： A semiconductor device includes a first semiconductor chip operating at a first power supply voltage and a second semiconductor chip operating at a second power supply voltage lower than the first power supply voltage to supply the second power supply voltage to the first semiconductor chip. The semiconductor chips according to the present invention are conveniently used for fabrication of the semiconductor device. The first semiconductor chip includes an output circuit including a first transistor and a second transistor, interconnected in series and turned on or off complementarily. The output circuit outputs a signal to a first external output terminal. The first semiconductor chip also includes a third transistor connected in series with the first and second transistors and having a gate electrode connected to a second output terminal. The entire chip area is reduced, as compared with the case where plural semiconductor chips, operated at different operating voltages, are interconnected and used as such in a semiconductor device provided with an input/output buffer operating at a voltage different from the respective operating voltages resulting in an increased chip area.

摘要翻译： 半导体器件包括以第一电源电压工作的第一半导体芯片和以低于第一电源电压的第二电源电压工作的第二半导体芯片，以向第一半导体芯片提供第二电源电压。 根据本发明的半导体芯片方便地用于制造半导体器件。 第一半导体芯片包括一个包括第一晶体管和第二晶体管的输出电路，其互相串联并互补地开或关。 输出电路将信号输出到第一外部输出端子。 第一半导体芯片还包括与第一和第二晶体管串联连接的第三晶体管，并且具有连接到第二输出端子的栅电极。 与在不同工作电压下工作的多个半导体芯片相互连接并将其用于半导体器件的情况相比，整个芯片面积减小，该半导体器件具有以不同于各个工作电压的电压工作的输入/输出缓冲器 导致芯片面积增加。

公开(公告)号：US20120223758A1

公开(公告)日：2012-09-06

申请号：US13037866

申请日：2011-03-01

申请人： Andreas Johannes Köllmann ,  Steffen Rode

发明人： Andreas Johannes Köllmann ,  Steffen Rode

IPC分类号： H03K5/08

CPC分类号： H03K19/018507 ,  H03K19/018592

摘要： Level-shifting devices and methods allow signals to be passed between input/output (I/O) ports. One such device comprises a first output driver that drives a first I/O port in response to a first control signal. A second output driver drives a second I/O port in response to a second control signal. A first comparator circuit, responsive to a first reference voltage and a voltage at the first I/O port, generates the second control signal. A limiter circuit limits driving of the second I/O port, by the second driver, to a limiting voltage that responsive to a the second I/O port over a first range of signaling voltages, and constrained to a set value over a second range. A voltage reference generating circuit generates a second reference voltage. A second comparator circuit generates the first control signal in response to the second reference voltage and the second I/O port.

摘要翻译： 电平转换装置和方法允许在输入/输出（I / O）端口之间传递信号。 一个这样的设备包括响应于第一控制信号驱动第一I / O端口的第一输出驱动器。 第二输出驱动器响应于第二控制信号驱动第二I / O端口。 响应于第一参考电压和第一I / O端口处的电压的第一比较器电路产生第二控制信号。 限制器电路将第二驱动器的第二I / O端口的驱动限制为在第一信号电压范围上响应于第二I / O端口的限制电压，并且限制在第二范围上的设定值 。 电压基准产生电路产生第二参考电压。 第二比较器电路响应于第二参考电压和第二I / O端口产生第一控制信号。

公开(公告)号：US07973562B1

公开(公告)日：2011-07-05

申请号：US12728777

申请日：2010-03-22

申请人： Yanbin Zhang ,  Look Thong Wong ,  Swee Meng Seow ,  Eng Tiong Soh

发明人： Yanbin Zhang ,  Look Thong Wong ,  Swee Meng Seow ,  Eng Tiong Soh

IPC分类号： H03K19/094

CPC分类号： H03K19/018585 ,  H03K19/018507 ,  H03K19/018592 ,  Y10T307/76 ,  Y10T307/977

摘要： An I/O module for an industrial controller provides single terminal outputs that may either sink or source current. This capability is provided through the use of dedicated sourcing and sinking transistors connected to the terminal and controlled by lockout logic ensuring activation of only the appropriate transistor in the correct phasing for sinking or sourcing operation modes.

摘要翻译： 用于工业控制器的I / O模块提供可能吸收或源电流的单端输出。 该功能是通过使用连接到端子的专用源极和吸收晶体管来实现的，并由锁定逻辑控制，以确保只有适当的晶体管才能激活正确的相位沉淀或采样操作模式。

公开(公告)号：US07932748B1

公开(公告)日：2011-04-26

申请号：US12640724

申请日：2009-12-17

申请人： Ming-Dou Ker ,  Yan-Liang Lin ,  Chua-Chin Wang

发明人： Ming-Dou Ker ,  Yan-Liang Lin ,  Chua-Chin Wang

IPC分类号： H03K19/0175

CPC分类号： H03K19/018592 ,  H03K19/00384 ,  H03K19/018507

摘要： A 2×VDD-tolerant input/output (I/O) buffer circuit with process, voltage, and temperature (PVT) compensation suitable for CMOS technology is disclosed. A 2×VDD-tolerant I/O buffer with a PVT compensation circuit is implemented with novel 2×VDD-tolerant logic gates. Output slew rate variations can be kept within smaller ranges to match maximum and minimum timing specifications. A 2×VDD tolerant logic circuit for implementing the I/O buffer is also disclosed.

公开(公告)号：US07702975B2

公开(公告)日：2010-04-20

申请号：US12099382

申请日：2008-04-08

申请人： Kevin W. Gorman ,  Michael R. Ouellette

发明人： Kevin W. Gorman ,  Michael R. Ouellette

IPC分类号： G01R31/28 ,  G11C29/00

CPC分类号： H03K19/018585 ,  H03K19/018557 ,  H03K19/018592

摘要： A method, an integrated circuit structure, and an associated design structure for the integrated circuit structure have a plurality of logic blocks, at least one of which is a redundant logic block. In addition, the structure includes a logic built-in self test device (LBIST) operatively connected to the logic blocks that determines the functionality of each of the logic blocks. An array of memory elements is included within the structure and is operatively connected to the logic blocks. At least one of the memory elements comprises a redundant memory element. The structure also includes an array built-in self test device (ABIST) operatively connected to the array of memory elements that determines the functionality of each of the memory elements. One feature is the use of a single controller operatively connected to the register, the logic blocks, and the memory elements. The single controller repairs both the logic blocks elements that have failing functionality and the memory elements that have failing functionality.

摘要翻译： 用于集成电路结构的方法，集成电路结构和相关联的设计结构具有多个逻辑块，其中至少一个是冗余逻辑块。 此外，该结构包括逻辑内置自检装置（LBIST），其可操作地连接到确定每个逻辑块的功能的逻辑块。 存储器元件阵列包括在结构内并且可操作地连接到逻辑块。 存储器元件中的至少一个包括冗余存储元件。 该结构还包括可操作地连接到确定每个存储器元件的功能的存储器元件阵列的阵列内置自检器件（ABIST）。 一个特征是使用可操作地连接到寄存器，逻辑块和存储器元件的单个控制器。 单个控制器修复具有故障功能的逻辑块元素和具有故障功能的存储器元件。

公开(公告)号：US20090243695A1

公开(公告)日：2009-10-01

申请号：US12060561

申请日：2008-04-01

申请人： Jeffrey M. THOMA

发明人： Jeffrey M. THOMA

IPC分类号： H03L5/00 ,  H03K17/28

CPC分类号： H03K19/018557 ,  H03K19/018592

摘要： The present example provides a circuit offering interoperability between circuits that may be powered from differing voltages, and that may operate at differing logic levels. Isolation may be provided from the impedance provided by transistor circuits and level shifting may be provided by a divider network. Accordingly, an exemplary slave and a master (or equivalently two circuits which are being coupled together) can operate on different voltages. This may be useful because some circuits such as processors can require higher or lower voltage than other processors that are sought to be coupled together. The circuit also may require one “read only” and another “input/output” pin, therefore, reducing the resources needed to implement the circuit functions. The present example can be useful for microprocessors that can use a software algorithm for the communications protocol, which can be economical to implement as it utilizes one input/output pin and one input only pin.

摘要翻译： 本示例提供了提供可由不同电压供电并且可以在不同逻辑电平下操作的电路之间的互操作性的电路。 可以从由晶体管电路提供的阻抗提供隔离，并且电平移位可以由分压网络提供。 因此，示例性从机和主机（或等效地两个正在耦合在一起的电路）可以在不同的电压上工作。 这可能是有用的，因为诸如处理器的一些电路可能需要比寻求耦合在一起的其它处理器更高或更低的电压。 该电路还可能需要一个“只读”引脚和另一个“输入/输出”引脚，因此减少了实现电路功能所需的资源。 本示例对于可以使用用于通信协议的软件算法的微处理器可能是有用的，当利用一个输入/输出引脚和一个仅输入引脚时，可以实现这些算法。