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    THREE STATE LATCH
    1.
    发明申请
    THREE STATE LATCH 审中-公开

    公开(公告)号：US20170207783A1

    公开(公告)日：2017-07-20

    申请号：US15476847

    申请日：2017-03-31

    申请人： Nvidia Corporation

    发明人： Andreas J. GOTTERBA ,  Jesse S. WANG

    IPC分类号： H03K19/00 ,  G11C7/06 ,  G11C11/419 ,  H03K3/038 ,  H03K19/094

    CPC分类号： H03K19/0002 ,  G11C7/065 ,  G11C11/419 ,  H03K3/038 ,  H03K19/09425

    摘要： Three state latch. In accordance with a first embodiment, an electronic circuit includes n pairs of cascaded logical gates. Each of the n pairs of cascaded logical gates includes a first logical gate including n−1 first gate inputs and one first gate output, and a second logical gate including two second gate inputs and one second gate output. One of the second gate inputs is coupled to the first gate output. The second gate output is cross coupled to one of the first gate inputs of all other the pairs of cascaded logical gates, and n is greater than 2.

    Sequential control circuit capable of sequencing through a number of stable states in a predetermined order
    2.
    发明授权
    Sequential control circuit capable of sequencing through a number of stable states in a predetermined order 失效
    顺序控制电路能够按预定顺序排列多个稳定状态

    公开(公告)号：US4105928A

    公开(公告)日：1978-08-08

    申请号：US743377

    申请日：1976-11-19

    申请人： Gilles Leconte

    发明人： Gilles Leconte

    IPC分类号： B60Q1/04 ,  B60Q1/14 ,  H03K3/038 ,  H03K17/62 ,  B60Q1/08 ,  H03K17/28

    CPC分类号： B60Q1/1407 ,  H03K17/6285 ,  H03K3/038

    摘要： A sequential control circuit capable of sequencing through a number of stable states in a predetermined order, starting from a predetermined stable state and sequencing in either of two opposite directions. A contact maker having two transient positions is connected to a timing circuit and to a logic circuit. In response to assumption by the contact maker of one of its transient positions, the timing circuit provides a timer signal delayed with respect to the interval of that transient position. The logic circuit sequences through a number of output conditions corresponding with the stable states in a direction determined by the particular transient position. The logic circuit includes circuitry for placing the circuit in a predetermined one of the output conditions upon initial start up.

    摘要翻译： 一种顺序控制电路，其能够以预定的顺序从预定的稳定状态开始并且以两个相反的方向中的任一个顺序从多个稳定状态排序。 具有两个瞬态位置的接触器连接到定时电路和逻辑电路。 响应于接触器对其瞬时位置之一的假设，定时电路提供相对于该瞬时位置的间隔延迟的定时器信号。 逻辑电路通过与由特定瞬态位置确定的方向上的稳定状态相对应的多个输出条件进行排序。 逻辑电路包括用于在初始启动时将电路放置在预定的一个输出条件中的电路。

    Automatic function setting and indication arrangement for a communications receiver
    3.
    发明授权
    Automatic function setting and indication arrangement for a communications receiver 失效
    通信接收机的自动功能设置和指示安排

    公开(公告)号：US4083012A

    公开(公告)日：1978-04-04

    申请号：US767377

    申请日：1977-02-10

    申请人： Willy Kanow

    发明人： Willy Kanow

    IPC分类号： H03J5/02 ,  H03K3/038 ,  H03H5/12

    CPC分类号： H03J5/0218 ,  H03K3/038

    摘要： A compact and efficient design of a function switching and indication arrangement for a TV receiver or other communications apparatus is described. The functional setting, illustratively indicative of a selected one of a plurality of TV channels, is chosen by the depression of an associated one of a plurality of keys that are respectively connected to externally accessible first switching terminals of a corresponding number of transistorized binary multivibrators that are arranged in an integrated circuit. The outputs of the multivibrators are coupled, on the integrated circuit chip, to a corresponding plurality of multi-collector transistors, one of whose outputs is used to reset the multivibrators of the non-selected channels, and another of whose outputs is employed to set the selected channel itself. A light emitting diode or other suitable visual indicator is connected in series with the key across the terminals of an energizing DC source, so that both such indicator and the key are coupled to a common access switching terminal of the associated multivibrator. The depression of the key serves simultaneously to provide a selection signal for the appropriate channel, to disable the multivibrator and indicator for each of the other channels, and to illuminate the indicator coupled to the depressed key.

    Three state latch
    7.
    发明授权
    Three state latch 有权

    公开(公告)号：US10009027B2

    公开(公告)日：2018-06-26

    申请号：US15476847

    申请日：2017-03-31

    申请人： Nvidia Corporation

    发明人： Andreas J. Gotterba ,  Jesse S. Wang

    IPC分类号： H03K19/00 ,  H03K3/038 ,  H03K19/094 ,  G11C11/419 ,  G11C7/06

    CPC分类号： H03K19/0002 ,  G11C7/065 ,  G11C11/419 ,  H03K3/038 ,  H03K19/09425

    摘要： Three state latch. In accordance with a first embodiment, an electronic circuit includes n pairs of cascaded logical gates. Each of the n pairs of cascaded logical gates includes a first logical gate including n−1 first gate inputs and one first gate output, and a second logical gate including two second gate inputs and one second gate output. One of the second gate inputs is coupled to the first gate output. The second gate output is cross coupled to one of the first gate inputs of all other the pairs of cascaded logical gates, and n is greater than 2.

    THREE STATE LATCH
    8.
    发明申请
    THREE STATE LATCH 审中-公开
    三态锁

    公开(公告)号：US20140354330A1

    公开(公告)日：2014-12-04

    申请号：US13909981

    申请日：2013-06-04

    申请人： Nvidia Corporation

    发明人： Andreas J. GOTTERBA ,  Jesse S. WANG

    IPC分类号： H03K19/00

    CPC分类号： H03K19/0002 ,  G11C7/065 ,  G11C11/419 ,  H03K3/038 ,  H03K19/09425

    摘要： In accordance with a first embodiment, an electronic circuit includes a single latch having three stable states. The electronic circuit may be configured so that all three outputs reflect a change at any one input in not more than three gate delays. The electronic circuit may further be configured so that when all inputs are set to one, a previous state of the latch is retained and output on the outputs.

    摘要翻译： 根据第一实施例，电子电路包括具有三个稳定状态的单个锁存器。 电子电路可以被配置为使得所有三个输出在不超过三个门延迟的情况下反映任何一个输入的变化。 电子电路还可以被配置为使得当所有输入被设置为1时，锁存器的先前状态被保持并输出到输出端。

    Semiconductor chip and semiconductor device
    9.
    发明授权
    Semiconductor chip and semiconductor device 有权
    半导体芯片和半导体器件

    公开(公告)号：US08350593B2

    公开(公告)日：2013-01-08

    申请号：US13015246

    申请日：2011-01-27

    申请人： Tomoaki Isozaki

    发明人： Tomoaki Isozaki

    IPC分类号： H03K19/0175 ,  H03K19/0185 ,  H03K19/094

    CPC分类号： H03K19/018592 ,  H01L25/07 ,  H01L27/092 ,  H01L29/78 ,  H01L2924/0002 ,  H03K3/038 ,  H03K19/018521 ,  H01L2924/00

    摘要： A semiconductor device includes a first semiconductor chip operating at a first power supply voltage and a second semiconductor chip operating at a second power supply voltage lower than the first power supply voltage to supply the second power supply voltage to the first semiconductor chip. The semiconductor chips according to the present invention are conveniently used for fabrication of the semiconductor device. The first semiconductor chip includes an output circuit including a first transistor and a second transistor, interconnected in series and turned on or off complementarily. The output circuit outputs a signal to a first external output terminal. The first semiconductor chip also includes a third transistor connected in series with the first and second transistors and having a gate electrode connected to a second output terminal. The entire chip area is reduced, as compared with the case where plural semiconductor chips, operated at different operating voltages, are interconnected and used as such in a semiconductor device provided with an input/output buffer operating at a voltage different from the respective operating voltages resulting in an increased chip area.

    摘要翻译： 半导体器件包括以第一电源电压工作的第一半导体芯片和以低于第一电源电压的第二电源电压工作的第二半导体芯片，以向第一半导体芯片提供第二电源电压。 根据本发明的半导体芯片方便地用于制造半导体器件。 第一半导体芯片包括一个包括第一晶体管和第二晶体管的输出电路，其互相串联并互补地开或关。 输出电路将信号输出到第一外部输出端子。 第一半导体芯片还包括与第一和第二晶体管串联连接的第三晶体管，并且具有连接到第二输出端子的栅电极。 与在不同工作电压下工作的多个半导体芯片相互连接并将其用于半导体器件的情况相比，整个芯片面积减小，该半导体器件具有以不同于各个工作电压的电压工作的输入/输出缓冲器 导致芯片面积增加。