公开(公告)号：US10886366B2

公开(公告)日：2021-01-05

申请号：US16258086

申请日：2019-01-25

申请人： SANDISK TECHNOLOGIES LLC

发明人： Noritaka Fukuo

IPC分类号： H01L29/06 ,  H01L27/11556 ,  H01L27/11582 ,  H01L21/765 ,  H01L27/11575 ,  H01L21/8234 ,  H01L27/11548

摘要： A semiconductor structure includes a device region including field effect transistors located on a semiconductor substrate, and a planarization dielectric layer overlying the field effect transistors. A hydrogen-blocking structure can be formed to prevent subsequent hydrogen diffusion into the device region. A moat trench is formed through the planarization dielectric layer and into the semiconductor substrate around the device region. A ring-shaped hydrogen-diffusion-blocking material portion is formed within the moat trench. A horizontally-extending portion of a silicon nitride diffusion barrier layer is formed over the planarization dielectric layer. The ring-shaped hydrogen-diffusion-blocking material portion may include a vertically-extending annular portion of the silicon nitride layer, or may include an annular metal portion that is formed prior to formation of the silicon nitride diffusion barrier layer.

公开(公告)号：US10861865B2

公开(公告)日：2020-12-08

申请号：US16561917

申请日：2019-09-05

申请人： Toshiba Memory Corporation

发明人： Yoshiaki Takahashi ,  Takahiro Tsurudo ,  Kiyofumi Sakurai

IPC分类号： G11C16/04 ,  H01L27/11573 ,  H01L27/11556 ,  H01L23/528 ,  H01L23/522 ,  H01L27/11526 ,  G11C16/24 ,  G11C11/56 ,  H01L27/11548 ,  H01L27/11575 ,  H01L27/11582 ,  G11C16/26

摘要： A semiconductor storage device includes first high-potential wirings, second high-potential wirings, a first low-potential wiring, a second low-potential wiring, a first branch wiring, and a second branch wiring formed in a wiring layer between a memory cell array and a semiconductor substrate and each extending in a first direction. The first branch wiring is electrically connected to the first low-potential wiring, and is adjacent to the first low-potential wiring on one side in a second direction perpendicular to the first direction of the first low-potential wiring. The second branch wiring is electrically connected to the second low-potential wiring, and is adjacent to the second low-potential wiring on the other side in the second direction of the second low-potential wiring. A first via is provided to contact the first branch wiring, and a second via is provided to contact the second branch wiring.

公开(公告)号：US20200373321A1

公开(公告)日：2020-11-26

申请号：US16708849

申请日：2019-12-10

申请人： SK hynix Inc.

发明人： Sung Kwang KWAK ,  Sang Woo PARK ,  Chang Woon CHOI

IPC分类号： H01L27/11575 ,  H01L27/11582 ,  H01L29/417 ,  H01L23/528

摘要： A semiconductor memory device includes a memory cell array disposed on a source plate; a discharge plate disposed on a bottom surface of the source plate; a source line discharge circuit disposed on a substrate below the discharge plate, and electrically coupling the discharge plate to a ground node in response to a source line discharge control signal; and a discharge path provided between the discharge plate and the source line discharge circuit.

公开(公告)号：US10833015B2

公开(公告)日：2020-11-10

申请号：US16879541

申请日：2020-05-20

申请人： MACRONIX INTERNATIONAL CO., LTD.

发明人： Shih-Hung Chen

IPC分类号： H01L23/528 ,  H01L27/11519 ,  H01L27/11575 ,  H01L27/11565 ,  H01L27/11548 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/1157

摘要： A memory device comprises a stack of linking elements including a first group of linking elements and a second group of linking elements different than the first group of linking elements. Interlayer connectors in a first plurality of interlayer connectors are connected to respective linking elements in the first group of linking elements. Interlayer connectors in a second plurality of interlayer connectors are connected to linking elements in the second group of linking elements. Patterned conductor lines in a first layer of patterned conductor lines are coupled to respective interlayer connectors in the first plurality of interlayer connectors. Patterned conductor lines in a second layer of patterned conductor lines disposed higher than the first layer of patterned conductor lines are coupled to respective interlayer connectors in the second plurality of interlayer connectors.

公开(公告)号：US10825865B2

公开(公告)日：2020-11-03

申请号：US16804810

申请日：2020-02-28

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Joyoung Park ,  Seok-Won Lee ,  Seongjun Seo

IPC分类号： H01L27/24 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11548 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/06

摘要： A three-dimensional semiconductor device is provided as follows. A substrate includes a contact region, a dummy region, and a cell array region. A stack structure includes electrodes vertically stacked on the substrate. The electrodes are stacked to have a first stepwise structure on the contact region and a second stepwise structure in the dummy region. Ends of at least two adjacent electrodes in the second stepwise structure have first sidewalls vertically aligned so that horizontal positions of the first sidewalls are substantially the same.

公开(公告)号：US10825832B2

公开(公告)日：2020-11-03

申请号：US16780999

申请日：2020-02-04

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Ji Mo Gu ,  Kyeong Jin Park ,  Hyun Mog Park ,  Byoung Il Lee ,  Tak Lee ,  Jun Ho Cha

IPC分类号： H01L27/11582 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11548 ,  H01L27/11524 ,  H01L27/1157

摘要： A semiconductor device includes first gate electrodes including a first lower electrode, a first upper electrode disposed above the first lower electrode and including a first pad region, and one or more first intermediate electrodes disposed between the first lower electrode and the first upper electrode. Second gate electrodes include a second lower electrode, a second upper electrode disposed above the second lower electrode, and one or more second intermediate electrodes disposed between the second lower electrode and the second upper electrode. The second gate electrodes are sequentially stacked above the first upper electrode, while exposing the first pad region. The first lower electrode extends by a first length, further than the first upper electrode, in a first direction. The second lower electrode extends by a second length, different from the first length, further than the second upper electrode, in the first direction.

公开(公告)号：US10811421B2

公开(公告)日：2020-10-20

申请号：US15712836

申请日：2017-09-22

申请人： Sang-yong Park ,  Kee-jeong Rho ,  Hyeong Park ,  Tae-wan Lim

发明人： Sang-yong Park ,  Kee-jeong Rho ,  Hyeong Park ,  Tae-wan Lim

IPC分类号： H01L27/108 ,  H01L27/1157 ,  H01L27/11575 ,  H01L23/31 ,  H01L23/528 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/423 ,  H01L29/78 ,  H01L29/792

摘要： Vertical memory devices, and methods of manufacturing the same, include providing a substrate including a cell array region and a peripheral circuit region, forming a mold structure in the cell array region, forming an opening for a common source line passing through the mold structure and extending in a first direction perpendicular to a top surface of the substrate, forming a first contact plug having an inner sidewall delimiting a recessed region in the opening for the common source line, and forming a common source bit line contact electrically connected to the inner sidewall of the first contact plug.

公开(公告)号：US10797144B2

公开(公告)日：2020-10-06

申请号：US16130432

申请日：2018-09-13

申请人： TOSHIBA MEMORY CORPORATION

发明人： Megumi Ishiduki ,  Hiroshi Nakaki ,  Takamasa Ito

IPC分类号： H01L29/423 ,  H01L29/66 ,  H01L27/11575 ,  H01L27/11582 ,  H01L27/11565 ,  H01L29/792 ,  H01L27/1157 ,  H01L27/11573 ,  H01L23/528

摘要： A semiconductor device includes a base body, a stacked body on the base body and a first columnar part. The base body includes a substrate, a first insulating film on the substrate, a first conductive film on the first insulating film, and a first semiconductor part on the first conductive film. The stacked body includes conductive layers and insulating layers stacked alternately in a stacking direction. The first columnar part is provided inside the stacked body and the first semiconductor part. The first columnar part includes a semiconductor body and a memory film between the semiconductor body and conductive layers. The semiconductor body extends in the stacking direction. The first columnar part has a first diameter and a second diameter in a first direction crossing the stacking direction. The first diameter inside the first semiconductor part is larger than the second diameter inside the stacked body.

公开(公告)号：US20200303416A1

公开(公告)日：2020-09-24

申请号：US16898720

申请日：2020-06-11

申请人： Samsung Electronics Co., Ltd.

发明人： Moon Kyu SONG ,  Ki Yoon KANG ,  Jae Hoon JANG

IPC分类号： H01L27/11582 ,  H01L23/00 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11551

摘要： A vertical memory device includes a substrate including a cell array region and a connection region adjacent to the cell array region, a plurality of gate electrode layers stacked on the cell array region and the connection region of the substrate, a channel structure on the cell array region and extending in a direction perpendicular to an upper surface of the substrate while penetrating through the plurality of gate electrode layers, a dummy channel structure on the connection region and extending in the direction perpendicular to the upper surface of the substrate while penetrating through at least a portion of the plurality of gate electrode layers, and a support insulating layer between a portion of the plurality of gate electrode layers and the dummy channel structure. The plurality of gate electrode form a stepped structure on the connection region.

公开(公告)号：US10784217B2

公开(公告)日：2020-09-22

申请号：US15906760

申请日：2018-02-27

申请人： TOSHIBA MEMORY CORPORATION

发明人： Hiroomi Nakajima

IPC分类号： H01L23/00 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573 ,  H01L23/535 ,  H01L27/11575

摘要： A memory device includes a circuit having an element on a substrate, an interconnection layer above the circuit and that includes a pad electrode having a region for metal wiring bonding, a plurality of electrode layers between the circuit and the interconnection layer and that are stacked in a first direction from the circuit to the interconnection layer, a semiconductor pillar that extends in the first direction, and a storage film between the electrode layers and the semiconductor pillar. The pad electrode overlaps the circuit element as viewed in the first direction.