公开(公告)号：US20250098170A1

公开(公告)日：2025-03-20

申请号：US18968053

申请日：2024-12-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kangmin Kim ,  Kyeong Jin Park ,  Seulji Lee ,  Hyejin Lee

IPC: H10B43/27 ,  G11C7/18 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

Abstract: A method of fabricating a semiconductor device is provided. The method includes: forming a mold structure, in which sacrificial layers and insulating layers are alternately stacked, on a substrate; forming trenches to penetrate the mold structure; forming first sacrificial patterns in the trenches; forming a first supporting layer on the mold structure and the first sacrificial patterns; forming vertical structures to penetrate the first supporting layer and the mold structure; forming a second supporting layer on the first supporting layer and on the vertical structures; forming openings to penetrate the first and second supporting layers and to expose the first sacrificial patterns; removing the first sacrificial patterns through the openings; and replacing the sacrificial layers with electrodes.

公开(公告)号：US11145669B2

公开(公告)日：2021-10-12

申请号：US16451385

申请日：2019-06-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joo Won Park ,  Kyeong Jin Park ,  Kwang Soo Kim

IPC: H01L27/11573 ,  H01L23/535 ,  H01L27/11582

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate and a stacked structure in which a plurality of insulating layers and a plurality of electrode layers are alternately stacked on the substrate. The semiconductor device includes a plurality of dummy channel structures that pass through the stacked structure. Moreover, the semiconductor device includes a contact structure in contact with at least one of the plurality of dummy channel structures adjacent thereto, and in contact with one of the plurality of electrode layers.

公开(公告)号：US20230309312A1

公开(公告)日：2023-09-28

申请号：US18299150

申请日：2023-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joo Won Park ,  Kyeong Jin Park ,  Kwang Soo Kim

IPC: H10B43/40 ,  H01L23/535 ,  H10B43/27

CPC classification number: H10B43/40 ,  H01L23/535 ,  H10B43/27

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate and a stacked structure in which a plurality of insulating layers and a plurality of electrode layers are alternately stacked on the substrate. The semiconductor device includes a plurality of dummy channel structures that pass through the stacked structure. Moreover, the semiconductor device includes a contact structure in contact with at least one of the plurality of dummy channel structures adjacent thereto, and in contact with one of the plurality of electrode layers.

公开(公告)号：US11094708B2

公开(公告)日：2021-08-17

申请号：US16378625

申请日：2019-04-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joo Won Park ,  Kyeong Jin Park

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  H01L29/423 ,  H01L23/48 ,  H01L21/28 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11519

Abstract: A vertical-type memory device includes a plurality of gate electrode layers spaced apart from one another and stacked on a substrate, and extending by different lengths in a first direction and forming a staircase structure, a first interlayer insulating layer covering the staircase structure of the plurality of gate electrode layers, and a plurality of gate contact plugs penetrating the interlayer insulating layer and respectively in contact with the gate electrode layers. The plurality of gate electrode layers include lower gate electrode layers disposed adjacently to the substrate, and upper gate electrode layers disposed on the lower gate electrode layers, so that the lower gate electrodes are between the substrate and the upper gate electrode layers. The plurality of gate contact plugs include lower gate contact plugs connected to the lower gate electrode layers, and upper gate contact plugs connected to the upper gate electrode layers. The upper gate contact plugs have top-most portions disposed at a height higher than a height of top surfaces of the lower gate contact plugs.

公开(公告)号：US10707231B2

公开(公告)日：2020-07-07

申请号：US16193283

申请日：2018-11-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyeong Jin Park ,  Seo-Goo Kang ,  Kwonsoon Jo ,  Kohji Kanamori

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L23/48 ,  H01L27/11568 ,  H01L23/528 ,  H01L23/522 ,  H01L29/10

Abstract: Disclosed is a semiconductor memory device comprising a peripheral circuit structure on a first substrate, a second substrate on the peripheral circuit structure, a stack structure on the second substrate and comprising a plurality of gate electrodes, a through dielectric pattern penetrating the stack structure and the second substrate, and a vertical supporter on a top surface of the second substrate and vertically extending from the top surface of the second substrate and penetrating the stack structure and the through dielectric pattern.

公开(公告)号：US12004353B2

公开(公告)日：2024-06-04

申请号：US18299150

申请日：2023-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joo Won Park ,  Kyeong Jin Park ,  Kwang Soo Kim

IPC: H10B43/40 ,  H01L23/535 ,  H10B43/27

CPC classification number: H10B43/40 ,  H01L23/535 ,  H10B43/27

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate and a stacked structure in which a plurality of insulating layers and a plurality of electrode layers are alternately stacked on the substrate. The semiconductor device includes a plurality of dummy channel structures that pass through the stacked structure. Moreover, the semiconductor device includes a contact structure in contact with at least one of the plurality of dummy channel structures adjacent thereto, and in contact with one of the plurality of electrode layers.

公开(公告)号：US11765900B2

公开(公告)日：2023-09-19

申请号：US17398455

申请日：2021-08-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joo Won Park ,  Kyeong Jin Park

IPC: H01L27/11582 ,  H01L27/11575 ,  H01L23/522 ,  H01L23/48 ,  H10B43/27 ,  H01L29/423 ,  H01L21/28 ,  H10B43/10 ,  H10B43/40 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40

CPC classification number: H10B43/27 ,  H01L23/481 ,  H01L29/40117 ,  H01L29/4234 ,  H10B43/10 ,  H10B43/40 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40

Abstract: A vertical-type memory device includes a plurality of gate electrode layers spaced apart from one another and stacked on a substrate, and extending by different lengths in a first direction and forming a staircase structure, a first interlayer insulating layer covering the staircase structure of the plurality of gate electrode layers, and a plurality of gate contact plugs penetrating the interlayer insulating layer and respectively in contact with the gate electrode layers. The plurality of gate electrode layers include lower gate electrode layers disposed adjacently to the substrate, and upper gate electrode layers disposed on the lower gate electrode layers, so that the lower gate electrodes are between the substrate and the upper gate electrode layers. The plurality of gate contact plugs include lower gate contact plugs connected to the lower gate electrode layers, and upper gate contact plugs connected to the upper gate electrode layers. The upper gate contact plugs have top-most portions disposed at a height higher than a height of top surfaces of the lower gate contact plugs.

公开(公告)号：US20220139952A1

公开(公告)日：2022-05-05

申请号：US17370507

申请日：2021-07-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kangmin Kim ,  Kyeong Jin Park ,  Seulji Lee ,  Hyejin Lee

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  G11C7/18 ,  H01L23/522

Abstract: A semiconductor device is disclosed. The semiconductor device may include gate stacks that are on a substrate, are spaced apart from each other in a first direction, and include electrodes and cell insulating layers alternately stacked, a separation structure between the gate stacks and extending in a second direction crossing the first direction, vertical structures penetrating the gate stacks and having conductive pads on upper portions thereof, a supporting structure on the gate stacks, bit lines on the supporting structure, and contact plugs penetrating the supporting structure and electrically connecting the bit lines to the vertical structures. A bottom surface of a portion of the supporting structure on the separation structure may be lower than top surfaces of the conductive pads.

公开(公告)号：US20220028878A1

公开(公告)日：2022-01-27

申请号：US17495320

申请日：2021-10-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joo Won Park ,  Kyeong Jin Park ,  Kwang Soo Kim

IPC: H01L27/11573 ,  H01L23/535 ,  H01L27/11582

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate and a stacked structure in which a plurality of insulating layers and a plurality of electrode layers are alternately stacked on the substrate. The semiconductor device includes a plurality of dummy channel structures that pass through the stacked structure. Moreover, the semiconductor device includes a contact structure in contact with at least one of the plurality of dummy channel structures adjacent thereto, and in contact with one of the plurality of electrode layers.

公开(公告)号：US12171097B2

公开(公告)日：2024-12-17

申请号：US17370507

申请日：2021-07-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kangmin Kim ,  Kyeong Jin Park ,  Seulji Lee ,  Hyejin Lee

IPC: H10B43/27 ,  G11C7/18 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor device is disclosed. The semiconductor device may include gate stacks that are on a substrate, are spaced apart from each other in a first direction, and include electrodes and cell insulating layers alternately stacked, a separation structure between the gate stacks and extending in a second direction crossing the first direction, vertical structures penetrating the gate stacks and having conductive pads on upper portions thereof, a supporting structure on the gate stacks, bit lines on the supporting structure, and contact plugs penetrating the supporting structure and electrically connecting the bit lines to the vertical structures. A bottom surface of a portion of the supporting structure on the separation structure may be lower than top surfaces of the conductive pads.