公开(公告)号：US07721300B2

公开(公告)日：2010-05-18

申请号：US10752853

申请日：2004-01-07

申请人： Daniel Eugene Tipton ,  Anantha Lakshmi Gangaraju ,  Ramesh Pusala

发明人： Daniel Eugene Tipton ,  Anantha Lakshmi Gangaraju ,  Ramesh Pusala

IPC分类号： G06F3/00 ,  G06F15/173 ,  G06F3/12

CPC分类号： H04L41/0893 ,  H04L41/06 ,  H04L41/082 ,  H04L41/22 ,  H04L43/0817 ,  H04L43/16

摘要： A system and method for managing a plurality of devices is provided. The system includes a user interface for controlling a plurality of devices configured as a network. The plurality of devices have corresponding device drivers to configure each of the plurality of devices to allow queuing operations to be performed in connection with the plurality of devices. The user interface is configured to communicate with the plurality of devices to identify and control jobs in a queue relating to each of the devices. The system also includes a monitoring system for monitoring the plurality of devices. The monitoring system is configured to provide notification to the user interface when a predetermined queue limit for at least one of the plurality of devices is exceeded.

摘要翻译： 提供了一种用于管理多个设备的系统和方法。 该系统包括用于控制被配置为网络的多个设备的用户界面。 多个设备具有对应的设备驱动器，以配置多个设备中的每一个以允许与多个设备相关地执行排队操作。 用户界面被配置为与多个设备通信以识别和控制与每个设备相关的队列中的作业。 该系统还包括用于监视多个设备的监视系统。 所述监视系统被配置为当超过所述多个设备中的至少一个设备的预定队列限制时，向所述用户界面提供通知。

公开(公告)号：US07433968B2

公开(公告)日：2008-10-07

申请号：US10388147

申请日：2003-03-12

申请人： Misty McCrea Chambers ,  David J. Hietanen ,  William Todd Shelton

发明人： Misty McCrea Chambers ,  David J. Hietanen ,  William Todd Shelton

IPC分类号： G06F15/177

CPC分类号： G05B19/056 ,  G05B2219/31104 ,  G05B2219/31418 ,  G05B2219/31422

摘要： An automation control module (ACM) includes an ACM central processing unit (CPU) and a file transfer system electrically connected to the ACM CPU. The file transfer system is embedded within the ACM, and is configured to receive at least one update for at least one module from a network and transfer the at least one update to the at least one module.

摘要翻译： 自动化控制模块（ACM）包括ACM中央处理单元（CPU）和与ACM CPU电连接的文件传输系统。 所述文件传输系统嵌入在所述ACM内，并被配置为从网络接收至少一个模块的至少一个更新，并将所述至少一个更新传送到所述至少一个模块。

公开(公告)号：US07240119B2

公开(公告)日：2007-07-03

申请号：US10065623

申请日：2002-11-04

申请人： Judy Dixon Ascoli ,  Paul Joseph O'Dea

发明人： Judy Dixon Ascoli ,  Paul Joseph O'Dea

IPC分类号： G06F15/16

CPC分类号： G05B19/056 ,  G05B2219/15012

摘要： A method for configuring a programmable logic controller (PLC) having a protocol is provided. The method includes providing an extensible markup language (XML) schema for the protocol of the PLC. In another aspect, a method for configuring a programmable logic controller (PLC) having a protocol includes utilizing the schema to validate at least one XML file parsed from a comma separated variable (CSV) file created by a configuration tool for a protocol different than the protocol of the PLC. In another aspect, a method for configuring a programmable logic controller (PLC) having a protocol includes utilizing the schema to validate at least one XML file parsed from a comma separated variable (CSV) file created by a configuration tool.

摘要翻译： 提供了一种用于配置具有协议的可编程逻辑控制器（PLC）的方法。 该方法包括为PLC协议提供可扩展标记语言（XML）架构。 在另一方面，一种用于配置具有协议的可编程逻辑控制器（PLC）的方法包括利用该模式来验证由配置工具创建的逗号分隔变量（CSV）文件解析的至少一个XML文件，用于不同于 PLC协议。 在另一方面，一种用于配置具有协议的可编程逻辑控制器（PLC）的方法包括利用所述模式来验证从由配置工具创建的逗号分隔变量（CSV）文件解析的至少一个XML文件。

公开(公告)号：US07143298B2

公开(公告)日：2006-11-28

申请号：US10124973

申请日：2002-04-18

申请人： Owen Newton Wells ,  Todd Philip Pfister

发明人： Owen Newton Wells ,  Todd Philip Pfister

IPC分类号： G11C11/406 ,  G06F1/26

CPC分类号： G06F1/30 ,  G06F11/1441

摘要： A memory module for a computer-based system. The memory module includes at least one memory device that requires periodic refresh signals to maintain data and is mounted on the memory module, and a circuit mounted on the memory module and configured to retain data stored on the memory device when the computer-based system loses power. In a separate embodiment, a control circuit is configured to logically detach at least one memory device from at least one memory controller when a computer-based system loses power, and retain data stored on the memory device when the computer-based system loses power.

公开(公告)号：US5473757A

公开(公告)日：1995-12-05

申请号：US989435

申请日：1992-12-11

申请人： Daniel W. Sexton

发明人： Daniel W. Sexton

IPC分类号： G06F13/24 ,  H04Q1/00

CPC分类号： G06F13/24

摘要： A programmable logic controller is provided in which I/O modules situated in respective slots are coupled to a CPU by a main bus including a serial data line. A dedicated slot enable line is provided from the CPU interrupt controller to each slot into which an I/O module may be positioned. In this manner, the CPU can enable a selected I/O module when desired. The I/O module includes an interrupt feature wherein an interrupt signal is provided to the same slot enable line which communicates a slot enable signal to the I/O module. The I/O module returns an interrupt on the slot enable line at times other than when the slot enable line is being used by the CPU interrupt controller to send a slot enable signal. The CPU interrupt controller includes an interrupt detection circuit which makes a determination of when two conditions simultaneously occur, namely when both a particular slot enable line is active and the CPU is not enabling the corresponding slot with the slot enable signal. The simultaneous occurrence of these conditions indicates that an interrupt is being received from the I/O module coupled to that slot enable line. By employing this apparatus and technique, the slot enable lines are shared by the CPU which uses the slot enable line to enable an I/O module and by the I/O module which uses the same slot enable line to communicate an interrupt to the CPU.

摘要翻译： 提供了一种可编程逻辑控制器，其中位于各个槽中的I / O模块通过包括串行数据线的主总线耦合到CPU。 从CPU中断控制器向I / O模块所在的每个插槽提供专用插槽使能线。 以这种方式，CPU可以在需要时启用所选择的I / O模块。 I / O模块包括中断特征，其中向与I / O模块通信时隙使能信号的相同的时隙使能线提供中断信号。 除了当CPU中断控制器正在使用时隙使能线发送时隙使能信号之外，I / O模块会在时隙使能线上返回中断。 CPU中断控制器包括中断检测电路，其确定何时同时发生两个条件，即当特定时隙使能线都处于活动状态并且CPU不启用具有时隙使能信号的相应时隙时。 这些条件的同时发生表明正在从耦合到该时隙使能线的I / O模块接收到中断。 通过采用该装置和技术，时隙使能线由CPU使用，CPU使用时隙使能线来使得I / O模块和使用相同时隙使能线的I / O模块向CPU传送中断 。

公开(公告)号：US5270916A

公开(公告)日：1993-12-14

申请号：US486063

申请日：1990-02-27

申请人： Daniel W. Sexton ,  Richard K. Davis

发明人： Daniel W. Sexton ,  Richard K. Davis

IPC分类号： G05B11/42 ,  G05B5/01 ,  G05B11/36

CPC分类号： G05B5/01

摘要： An apparatus and method are provided for preventing the runaway of the integral term of a proportional integral differential controller which is usable in a feedback system. An error signal is supplied to the controller by the feedback system. The controller produces a control variable output signal from the error signal. In accordance with the invention, the controller imposes a slew rate limit on the control variable output signal. Also in accordance with the invention, whenever the controller attempts to drive the control variable output signal to exceed the slew rate limit, the integral term associated with the controller is adjusted to a value which forces the control variable output signal to its slew rate limited value. In this manner, runaway of the integral term associated with the controller is desirably avoided.

摘要翻译： 提供了一种用于防止在反馈系统中可用的比例积分微分控制器的积分项失控的装置和方法。 误差信号由反馈系统提供给控制器。 控制器从误差信号产生一个控制变量输出信号。 根据本发明，控制器对控制变量输出信号施加压摆率限制。 同样根据本发明，每当控制器试图驱动控制变量输出信号超过转换速率极限时，与控制器相关联的积分项被调整到一个值，该值将控制变量输出信号强制到其转换速率限制值 。 以这种方式，期望避免与控制器相关联的积分项的失控。

公开(公告)号：US5109503A

公开(公告)日：1992-04-28

申请号：US355266

申请日：1989-05-22

申请人： Ancil B. Cruickshank ,  Richard K. Davis

发明人： Ancil B. Cruickshank ,  Richard K. Davis

IPC分类号： G05B19/05 ,  H03K19/177 ,  H03K21/00

CPC分类号： H03K21/00

摘要： A reconfigurable counter is provided which includes first and second memories coupled via a common bus to a microprocessor which controls the process of configuring and reconfiguring the counter. A programmable hardware array, coupled to the microprocessor, is capable of being programmed to emulate a plurality of different counter types. The first memory stores a plurality of different counter configuration profiles, each of which corresponds to a different type counter configuraiton. In one or more of the selected counter types, different counter modes such as an up-down counter mode, pulse direction counter mode and A quad B counter modes are available. When the user indicates a selected counter profile to the microprocessor, the microprocessor writes the corresponding counter configuration profile from the first memory into the programmable hardware array using the parameters or modes of operation stored in the second memory until such time as the user indicates the choice of another counter profile to the microprocessor.

摘要翻译： 提供了一种可重构计数器，其包括通过公共总线耦合到微处理器的第一和第二存储器，微处理器控制配置和重新配置计数器的过程。 耦合到微处理器的可编程硬件阵列能够被编程为模拟多个不同的计数器类型。 第一存储器存储多个不同的计数器配置配置文件，每个配置配置文件对应于不同类型的计数器配置。 在一个或多个选择的计数器类型中，可以使用不同的计数器模式，例如升降计数器模式，脉冲方向计数器模式和A quad B计数器模式。 当用户向微处理器指示选择的计数器配置文件时，微处理器使用存储在第二存储器中的参数或操作模式将相应的计数器配置简档从第一存储器写入可编程硬件阵列，直到用户指示选择 的另一个计数器配置文件到微处理器。

公开(公告)号：US5056001A

公开(公告)日：1991-10-08

申请号：US453655

申请日：1989-12-20

申请人： Daniel W. Sexton

发明人： Daniel W. Sexton

IPC分类号： G06F9/06 ,  G05B9/05 ,  G05B19/05

CPC分类号： G05B19/054 ,  G05B2219/1109 ,  G05B2219/1131 ,  G05B2219/1139 ,  G05B2219/1141 ,  G05B2219/1196 ,  G05B2219/14052

摘要： A method is provided for configuring a smart module which is coupled to a programmable logic controller. The controller includes an initial configuration file which specifies an initial configuration for the smart module. After power up and initialization of the controller, the initial configuration file is transmitted from the controller to the smart module. The initial configuration file is now designated a current configuration file and the smart module assumes the configuration specified by the current configuration file. In accordance with the method of the invention, module specific information which is stored in the module is then displayed to aid a user in configuring the module. The user can then modify the current configuration file in response to the module specific information which was displayed. This method significantly simplifies the process of configuring smart modules for the user.

公开(公告)号：US4979122A

公开(公告)日：1990-12-18

申请号：US304530

申请日：1989-02-01

申请人： Richard K. Davis ,  Keith W. Curtin

发明人： Richard K. Davis ,  Keith W. Curtin

IPC分类号： G01R21/133

CPC分类号： G01R21/1331

摘要： A power monitor, for determining real and imaginary power associated with one or more line signals, samples a plurality of line cycles during an observation window to generate a plurality of voltage-current sample sets for each line cycle. The sampling of the sample sets is timed such that the voltage-current sample sets are taken at different relative time positions. The power monitor stores incoming voltage-current sample data in one memory area and concurrently analyzes sample data already stored in another memory area. Deletion of sample data is not permitted until transient analysis of such data is complete.In another embodiment, the power monitor includes a working data memory area coupled to the sampling circuitry such that the sample sets occurring during each observation window are stored in the working data memory area in interleaved fashion to simulate a single cycle of data. This power monitor further includes a transient data area, coupled to the sampling circuitry, for storing the sample sets occurring during an observation window in a non-interleaved or sequential fashion. Power analysis is conducted on the sample sets in the working data memory area unless a power transient is sensed. Upon sensing a transient, data from the transient data area is provided for analysis.

摘要翻译： 用于确定与一个或多个线路信号相关联的实际和虚拟功率的功率监视器，在观察窗口期间采样多个线路周期，以便为每个线路周期生成多个电压 - 电流采样组。 样本集的采样被定时，使得电压 - 电流采样集在不同的相对时间位置拍摄。 电源监视器将输入的电压 - 电流采样数据存储在一个存储器区域中，并且同时分析已经存储在另一存储器区域中的采样数据。 除非这些数据的瞬时分析完成，否则不允许删除样本数据。 在另一个实施例中，功率监视器包括耦合到采样电路的工作数据存储区域，使得在每个观察窗口期间发生的采样集合以交错方式存储在工作数据存储区域中以模拟单个周期的数据。 该功率监视器还包括耦合到采样电路的瞬态数据区，用于以非交错或顺序方式存储在观察窗期间发生的采样集。 对工作数据存储区域中的样本集进行功率分析，除非检测到电源瞬态。 在感测瞬态时，提供来自瞬态数据区的数据用于分析。

公开(公告)号：US07904583B2

公开(公告)日：2011-03-08

申请号：US10617551

申请日：2003-07-11

申请人： Robert Baxter Chambers, II ,  Ferrell Mercer

发明人： Robert Baxter Chambers, II ,  Ferrell Mercer

IPC分类号： G06F15/16

CPC分类号： G06F17/30893

摘要： A web-enabled automation control module (ACM) system includes at least one network module configured to receive a request for a file from the network, a web server and database module located outside the network module and including a database configured to store the file, and an ACM central processing unit (CPU) configured to send ACM data to the web server and database module to embed ACM data in the file.

摘要翻译： 网络自动化控制模块（ACM）系统包括至少一个网络模块，其被配置为从网络接收对文件的请求，位于网络模块外部的web服务器和数据库模块，并且包括被配置为存储文件的数据库， 以及ACM中央处理单元（CPU），其配置为向Web服务器和数据库模块发送ACM数据以将ACM数据嵌入到文件中。