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公开(公告)号：US12133477B2
公开(公告)日：2024-10-29
申请号：US17873594
申请日：2022-07-26
发明人： Zezhi Chen , Zhichao Lu , Liang Zhao
CPC分类号： H10N70/245 , G11C13/0007 , G11C13/0011 , H10N70/826 , H10N70/883
摘要： A resistive random access memory (RRAM) and a method for operating the RRAM are disclosed. The RRAM includes at least two successively stacked conductive layers and a resistive switching layer situated between every adjacent two conductive layers, wherein a migration interface with an interface effect is formed at each interface between one conductive layer and the resistive switching layer in contact therewith, wherein the migration interface regulates, by the interface effect, vacancies formed in the resistive switching layer under the effect of an electrical signal. The regulation includes at least one of absorption, migration and diffusion.
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公开(公告)号：US11887645B2
公开(公告)日：2024-01-30
申请号：US18082005
申请日：2022-12-15
发明人： Zhichao Lu , Liang Zhao
CPC分类号： G11C11/2273 , G06N3/06 , G06N5/04 , G11C11/2255 , G11C11/2257 , G11C11/4074 , G11C11/5642
摘要： Dual-precision analog memory cells and arrays are provided. In some embodiments, a memory cell, comprises a non-volatile memory element having an input terminal and at least one output terminal; and a volatile memory element having a plurality of input terminals and an output terminal, wherein the output terminal of the volatile memory element is coupled to the input terminal of the non-volatile memory element, and wherein the volatile memory element comprises: a first transistor coupled between a first supply and a common node, and a second transistor coupled between a second supply and the common node; wherein the common node is coupled to the output terminal of the volatile memory element; and wherein gates of the first and second transistors are coupled to respective ones of the plurality of input terminals of the volatile memory element.
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公开(公告)号：US20230307045A1
公开(公告)日：2023-09-28
申请号：US18205417
申请日：2023-06-02
发明人： Brent HAUKNESS , Zhichao LU
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/0026 , G11C13/0028 , G11C13/003 , G11C2013/0078 , G11C2013/0092 , G11C2213/82
摘要： Disclosed is a resistive random access memory (RRAM) circuit and related method to limit current, or ramp voltage, applied to a source line or bitline of an RRAM array. The RRAM array has one or more source lines and one or more bitlines. A control circuit sets an RRAM cell to a low resistance state in a set operation, and resets the RRAM cell to a high resistance state in a reset operation. A voltage applied to a bitline or source line is ramped during a first time interval, held to a maximum voltage value during a second interval, and ceased after the second time interval.
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公开(公告)号：US11682457B2
公开(公告)日：2023-06-20
申请号：US17536386
申请日：2021-11-29
发明人： Brent Haukness , Zhichao Lu
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/003 , G11C13/0026 , G11C13/0028 , G11C2013/0078 , G11C2013/0092 , G11C2213/82
摘要： A resistive random access memory (RRAM) circuit and related method limits current, or ramp voltage, applied to a source line or bitline of an RRAM array. The RRAM array has one or more source lines and one or more bitlines. A control circuit sets an RRAM cell to a low resistance state in a set operation, and resets the RRAM cell to a high resistance state in a reset operation. A voltage applied to a bitline or source line is ramped during a first time interval, held to a maximum voltage value during a second interval, and ceased after the second time interval.
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公开(公告)号：US20220328000A1
公开(公告)日：2022-10-13
申请号：US17642551
申请日：2020-08-12
发明人： Ximeng GUAN
IPC分类号： G09G3/3233
摘要： A display driver integrated circuit includes an input port configured to receive a display sensing signal for a display panel; a resistive random access memory coupled to the input port and configured to store a sensing value indicative of the display sensing signal; a display compensation logic coupled to the resistive random access memory to receive the sensing value and configured to determine, based on the sensing value, a compensation value to enable the display panel to modify a display control signal; and an output port coupled to the display compensation logic to transmit a display compensation voltage signal to the display panel. The display compensation voltage signal is generated based on the compensation value.
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公开(公告)号：US11348652B2
公开(公告)日：2022-05-31
申请号：US17078496
申请日：2020-10-23
发明人： Liang Zhao
摘要： The disclosed embodiments provide neural network inference accelerator based on one-time-programmable (OTP) memory arrays with one-way selectors. In some embodiments, a memory array may comprise: a plurality of one-time-programmable memory cells each comprising: a one-time-programmable memory element; a top electrode having an upper surface in contact with the one-time-programmable memory element; a dielectric layer in contact with a lower surface of the top electrode; a bottom electrode; and a dense layer having an upper surface in contact with the dielectric layer, and a lower surface in contact with the bottom electrode, wherein the dense layer comprises Al2O3 or MgO.
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公开(公告)号：US11152062B2
公开(公告)日：2021-10-19
申请号：US17008505
申请日：2020-08-31
IPC分类号： G11C13/00 , G11C5/06 , G11C5/02 , G11C11/419 , G11C11/16
摘要： A memory device comprises: an array of memory cells arranged in a plurality of columns in a first direction and a plurality of rows in a second direction, wherein each memory cell in the array comprises: a select transistor, wherein a source terminal of the select transistor is coupled to a source line, and wherein a gate terminal of the select transistor is coupled to a word line, and a memory element coupled in series with the select transistor, wherein a first end of the memory element is coupled to a drain terminal of the select transistor, and wherein a second end of the memory element is coupled to a bit line; and a control circuit configured to provide an unselected source line voltage to source lines of unselected memory cells before providing a selected word line voltage to a word line of a selected memory cell.
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公开(公告)号：US20210295911A1
公开(公告)日：2021-09-23
申请号：US17244507
申请日：2021-04-29
发明人： Danut MANEA
IPC分类号： G11C13/00
摘要： Circuits and methods are disclosed for voltage-mode bit line precharge for random-access memory cells. A circuit includes an array of random access memory cells; a low-impedance voltage source configured to provide a precharge voltage; and a control circuit configured to precharge a bit line of one of the random access memory cells to the precharge voltage using the low-impedance voltage source prior to reading the one of the random access memory cells.
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公开(公告)号：US20210257014A1
公开(公告)日：2021-08-19
申请号：US17308675
申请日：2021-05-05
发明人： Zhichao LU , Liang ZHAO
IPC分类号： G11C11/22 , G06N5/04 , G11C11/56 , G06N3/06 , G11C11/4074
摘要： Dual-precision analog memory cells and arrays are provided. In some embodiments, a memory cell, comprises a non-volatile memory element having an input terminal and at least one output terminal; and a volatile memory element having a plurality of input terminals and an output terminal, wherein the output terminal of the volatile memory element is coupled to the input terminal of the non-volatile memory element, and wherein the volatile memory element comprises: a first transistor coupled between a first supply and a common node, and a second transistor coupled between a second supply and the common node; wherein the common node is coupled to the output terminal of the volatile memory element; and wherein gates of the first and second transistors are coupled to respective ones of the plurality of input terminals of the volatile memory element.
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公开(公告)号：US20210082504A1
公开(公告)日：2021-03-18
申请号：US16670633
申请日：2019-10-31
发明人： Danut MANEA
IPC分类号： G11C13/00
摘要： Circuits and methods are disclosed for voltage-mode bit line precharge for random-access memory cells. A circuit includes an array of random access memory cells; a low-impedance voltage source configured to provide a precharge voltage; and a control circuit configured to precharge a bit line of one of the random access memory cells to the precharge voltage using the low-impedance voltage source prior to reading the one of the random access memory cells.
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