公开(公告)号：US20230019326A1

公开(公告)日：2023-01-19

申请号：US17945676

申请日：2022-09-15

申请人： HEFEI RELIANCE MEMORY LIMITED

发明人： Danut MANEA

IPC分类号： G11C13/00

摘要： Circuits and methods are disclosed for voltage-mode bit line precharge for random-access memory cells. A circuit includes an array of random access memory cells; a low-impedance voltage source configured to provide a precharge voltage; and a control circuit configured to precharge a bit line of one of the random access memory cells to the precharge voltage using the low-impedance voltage source prior to reading the one of the random access memory cells.

公开(公告)号：US20230018760A1

公开(公告)日：2023-01-19

申请号：US17948712

申请日：2022-09-20

申请人： HEFEI RELIANCE MEMORY LIMITED

发明人： Liang ZHAO ,  Zhichao LU

IPC分类号： H01L45/00 ,  H01L27/24

摘要： Thermal field controlled electrical conductivity change devices and applications therefore are provided. In some embodiments, a thermal switch, comprises: a metal-insulator-transition (MIT) material; first and second terminals electrically coupled to the MIT material; and a heater disposed near the MIT material.

公开(公告)号：US20230012275A1

公开(公告)日：2023-01-12

申请号：US17948419

申请日：2022-09-20

申请人： Hefei Reliance Memory Limited

发明人： Zhichao LU ,  Brent HAUKNESS ,  Gary BRONNER

IPC分类号： G11C13/00 ,  G11C29/12

摘要： The embodiments herein describe technologies of initializing resistive memory devices (e.g., non-volatile and volatile memory devices). In one method, a first voltage is applied across a resistance change material of a memory cell to form an initial filament and multiple cycles are performed to condition the initial filament. Each of the multiple cycles includes: applying a second voltage with a first polarity across the resistance change material; and applying a third voltage with a second polarity across the resistance change material.

公开(公告)号：US11502249B2

公开(公告)日：2022-11-15

申请号：US17028909

申请日：2020-09-22

申请人： Hefei Reliance Memory Limited

发明人： Christophe J. Chevallier ,  Steve Kuo-Ren Hsia ,  Wayne Kinney ,  Steven Longcor ,  Darrell Rinerson ,  John Sanchez ,  Philip F. S. Swab ,  Edmond R. Ward

IPC分类号： H01L45/00 ,  H01L27/24 ,  G11C11/56 ,  G11C13/00 ,  G11C11/16

摘要： A re-writeable non-volatile memory device including a re-writeable non-volatile two-terminal memory element (ME) having tantalum. The ME including a first terminal, a second terminal, a first layer of a conductive metal oxide (CMO), and a second layer in direct contact with the first layer. The second layer and the first layer being operative to store at least one-bit of data as a plurality of resistive states, and the first and second layer are electrically in series with each other and with the first and second terminals.

公开(公告)号：US11335636B2

公开(公告)日：2022-05-17

申请号：US17079363

申请日：2020-10-23

申请人： HEFEI RELIANCE MEMORY LIMITED

发明人： Liang Zhao

IPC分类号： G11C17/18 ,  H01L23/525 ,  H01L27/112 ,  G11C17/16 ,  G11C11/56

摘要： The disclosed embodiments provide gradual breakdown memory cell having multiple different dielectrics. In some embodiments, a multi-level one-time-programmable memory cell, comprises: a top electrode; a bottom electrode; and a plurality of dielectric layers disposed between the top and bottom electrodes, wherein at least one of the following is true: at least two of the dielectric layers are of different dielectric materials; and the multi-level one-time-programmable memory cell comprises at least one metal layer, wherein each metal layer is disposed between two of the dielectric layers.

公开(公告)号：US20220130459A1

公开(公告)日：2022-04-28

申请号：US17571094

申请日：2022-01-07

申请人： HEFEI RELIANCE MEMORY LIMITED

发明人： Deepak Chandra SEKAR ,  Gary Bela BRONNER ,  Frederick A. WARE

IPC分类号： G11C13/00

摘要： A memory cell includes a first resistive memory element, a second resistive memory element electrically coupled with the first resistive memory element at a common node, and a switching element comprising an input terminal electrically coupled with the common node, the switching element comprising a driver configured to float during one or more operations.

公开(公告)号：US20220093856A1

公开(公告)日：2022-03-24

申请号：US17540486

申请日：2021-12-02

申请人： HEFEI RELIANCE MEMORY LIMITED

发明人： Zhiqiang WEI ,  Zhichao LU

IPC分类号： H01L45/00 ,  H01L27/24 ,  G11C13/00

摘要： A non-volatile memory cell includes a bottom electrode, a top electrode having a conductive material, a resistive layer interposed between the bottom electrode and the top electrode, and side portions covering sides of the top electrode and the resistive layer. The side portions contain an oxide of the conductive material. The non-volatile memory cell further includes a contact wire disposed on the top electrode. A width of the contact wire is less than a width between lateral outer surfaces of the side portions.

公开(公告)号：US11238930B2

公开(公告)日：2022-02-01

申请号：US16984043

申请日：2020-08-03

申请人： Hefei Reliance Memory Limited

发明人： Brent Haukness ,  Zhichao Lu

IPC分类号： G11C13/00

摘要： Disclosed is a resistive random access memory (RRAM) circuit and related method to limit current, or ramp voltage, applied to a source line or bitline of an RRAM array. The RRAM array has one or more source lines and one or more bitlines. A control circuit sets an RRAM cell to a low resistance state in a set operation, and resets the RRAM cell to a high resistance state in a reset operation. A voltage applied to a bitline or source line is ramped during a first time interval, held to a maximum voltage value during a second interval, and ceased after the second time interval.

公开(公告)号：US20210295913A1

公开(公告)日：2021-09-23

申请号：US17338494

申请日：2021-06-03

申请人： Hefei Reliance Memory Limited

发明人： Deepak Chandra SEKAR ,  Wayne Frederick ELLIS ,  Brent Steven HAUKNESS ,  Gary Bela BRONNER ,  Thomas VOGELSANG

IPC分类号： G11C13/00 ,  G11C7/08 ,  G11C8/10

摘要： Provided are a device comprising a bit cell tile including at least two memory cells, each of the at least two memory cells including a resistive memory element, and methods of operating an array of the memory cells, each memory cell including a resistive memory element electrically coupled in series to a corresponding first transistor and to a corresponding second transistor, the first transistor including a first gate coupled to a corresponding one of a plurality of first word lines and the second transistor including a second gate coupled to a corresponding one of a plurality of second word lines, each memory cell coupled between a corresponding one of a plurality of bit lines and a corresponding one of a plurality of source lines. The methods may include applying voltages to the first word line, second word line, source line, and bit line of a memory cell selected for an operation, and resetting the resistive memory element of the memory cell in response to setting the selected bit line to ground.

公开(公告)号：US11081168B2

公开(公告)日：2021-08-03

申请号：US16876616

申请日：2020-05-18

申请人： HEFEI RELIANCE MEMORY LIMITED

发明人： Liang Zhao ,  Zhichao Lu

IPC分类号： G11C7/00 ,  G11C11/4094 ,  G11C11/408 ,  G11C11/4091 ,  G11C5/06 ,  G06F21/60 ,  G11C5/05

摘要： A non-volatile memory device includes a plurality of memory cells arranged in a matrix, a plurality of word lines extended in a row direction, and a plurality of bit lines extended in a column direction. Each of the memory cells is coupled to one of the word lines and one of the bit lines. The memory device further includes a word-line control circuit coupled to and configured to control the word lines, a first bit-line control circuit configured to control the bit lines and sense the memory cells in a digital mode, and a second bit-line control circuit configured to bias the bit lines and sense the memory cells in an analog mode. The first bit-line control circuit is coupled to a first end of each of the bit lines. The second bit-line control circuit is coupled to a second end of each of the bit lines.