公开(公告)号：US6004851A

公开(公告)日：1999-12-21

申请号：US42213

申请日：1998-03-13

Applicant: Chun-Hung Peng

Inventor： Chun-Hung Peng

IPC: H01L21/266 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L29/6659 ,  H01L21/266 ,  H01L29/6656 ,  H01L29/7833

Abstract: A method for manufacturing a metal-oxide-semico nductor field effect transistor (MOSFET) having a drain and a source each of which has a lightly doped area, an enhanced lightly doped area and a heavily doped area is disclosed. The method includes steps of lightly doping the silicon substrate having a gate structure to form the lightly doped areas of the source and the drain; forming a first non-conductive layer covering the silicon substrate and the gate, forming a second non-conductive layer covering the first non-conductive layer, forming a duple-sidewall including a side-wall-spacer of the first non-conductive layer and an inner spacer, heavily doping the silicon substrate to form the heavily doped areas of the source and the drain respectively, removing the side-wall-spacer of the first non-conductive layer, executing an anisotropic etching on the inner spacer to form a cascade-shaped spacer of the gate, and doping the silicon substrate to form the enhanced lightly doped area and thus forming the extension area of the heavily doped area.

Abstract translation: 公开了一种制造具有漏极和源极的金属氧化物 - 半导体场效应晶体管（MOSFET）的方法，每个漏极和源极具有轻掺杂区域，增强的轻掺杂区域和重掺杂区域。 该方法包括以下步骤：轻掺杂具有栅极结构的硅衬底，以形成源极和漏极的轻掺杂区域; 形成覆盖所述硅衬底和所述栅极的第一非导电层，形成覆盖所述第一非导电层的第二非导电层，形成包括所述第一非导电层的侧壁间隔物的双面侧壁，以及 内部间隔物，重掺杂硅衬底以分别形成源极和漏极的重掺杂区域，去除第一非导电层的侧壁间隔物，在内部间隔物上执行各向异性蚀刻以形成级联 并掺杂硅衬底以形成增强的轻掺杂区域，从而形成重掺杂区域的扩展区域。

公开(公告)号：US5878096A

公开(公告)日：1999-03-02

申请号：US826066

申请日：1997-03-24

Applicant: Hsuan Ming Shao ,  Yi Ren Chen

Inventor： Hsuan Ming Shao ,  Yi Ren Chen

IPC: H04J3/06 ,  H04L7/02 ,  H04L7/00

CPC classification number: H04L7/0029 ,  H04L7/10

Abstract: Disclosed is a digital filter having phase-adjustment ability, and more particularly to a digital filter system which can restore the phase of data transmitted via digital radio communication and thereby enhances the noise-immunity of data and the correct bit decision. The digital filter mainly includes a hold back data unit, a digital filter unit, and a signal phase modify unit to remove noises in the signals and to modify and restore correct digital wave-form signals. The digital filter having phase-adjustment ability is suitable for use in digital radio phones, pagers, etc. commonly found in the radio communication systems.

Abstract translation: 公开了具有相位调整能力的数字滤波器，更具体地说，涉及一种数字滤波器系统，其可以恢复经由数字无线电通信发送的数据的相位，从而增强了数据的抗噪声性和正确的位决定。 数字滤波器主要包括保持数据单元，数字滤波器单元和信号相位修改单元，以消除信号中的噪声并修改和恢复正确的数字波形信号。 具有相位调整能力的数字滤波器适用于无线电通信系统中常见的数字无线电话，寻呼机等。

公开(公告)号：US5777919A

公开(公告)日：1998-07-07

申请号：US713741

申请日：1996-09-13

Applicant: Wu Chi-Yung ,  Ling Chen ,  Tony Peng

Inventor： Wu Chi-Yung ,  Ling Chen ,  Tony Peng

IPC: G11C7/18 ,  G11C17/12 ,  H01L27/115 ,  G11C17/00

CPC classification number: H01L27/115 ,  G11C17/126 ,  G11C7/18

Abstract: The present invention is related to an enhanced high density Read-Only-Memory (ROM) device with select gate. A thin oxide layer is deposited on the ROM cell matrix and it is extended to the select lines which is on the top and bottom side of the ROM cell matrix to form the select gate. The ROM cell matrix can be organized more flexible by using the buried layers to pick out the unwanted gates. The metal contact can be directly made in this extended region too. Thereafter it reduces the manufacturing cost and achieves a high speed and density and simple process device.

Abstract translation: 本发明涉及具有选择门的增强型高密度只读存储器（ROM）器件。 在ROM单元矩阵上沉积薄的氧化物层，并将其延伸到位于ROM单元矩阵的顶部和底部的选择线以形成选择栅极。 通过使用埋层挑出不想要的栅极，ROM单元矩阵可以更灵活地组织起来。 金属接触可以直接在这个扩展区域制造。 此后，它降低了制造成本，并实现了高速度和密度以及简单的工艺装置。

公开(公告)号：US5754806A

公开(公告)日：1998-05-19

申请号：US552217

申请日：1995-11-03

Applicant: Kuo Cheng Yu

Inventor： Kuo Cheng Yu

IPC: G06F9/26 ,  G06F9/30 ,  G06F9/312 ,  G06F9/38

CPC classification number: G06F9/3004 ,  G06F9/262 ,  G06F9/383

Abstract: A memory table look-up method for executing a table look-up instruction in an active program uses an instruction buffer executing device, a controller and a data register to output table look-up data from a memory to the data register. The method includes causing an instruction buffer executing device to execute a table look-up instruction obtained from the memory and pre-stored in the instruction buffer executing device in a first cycle to generate and output a table look-up signal, and to cause the controller to output a next instruction being an instruction next to the table look-up instruction in the active program from the memory to the instruction buffer executing device in response to the table look-up signal. The method further includes the step of causing the controller to generate a forbidding signal in a second cycle for latching the next instruction located in the instruction buffer executing device, and to generate and output a write-in instruction to the instruction buffer executing device for generating a write-in signal in order to output said table look-up data to the data register.

Abstract translation: 用于在活动程序中执行表查找指令的存储器表查找方法使用指令缓冲器执行装置，控制器和数据寄存器来将表查询数据从存储器输出到数据寄存器。 该方法包括使指令缓冲器执行装置执行从存储器获得并在第一周期中预先存储在指令缓冲执行装置中的表查找指令，以产生并输出表查找信号，并使 控制器，用于响应于表查找信号，从存储器向指令缓冲器执行装置输出下一条指令，该指令是与活动程序中的表查找指令相邻的指令。 该方法还包括使控制器在第二周期中产生禁止信号以锁存位于指令缓冲器执行装置中的下一个指令的步骤，并且生成并将写入指令输出到指令缓冲器执行装置，以产生 写入信号，以便将所述表查找数据输出到数据寄存器。

公开(公告)号：US5714954A

公开(公告)日：1998-02-03

申请号：US574393

申请日：1995-12-18

Applicant: Herman Chung ,  Rong-Tyan Wu

Inventor： Herman Chung ,  Rong-Tyan Wu

IPC: G06F1/03 ,  H03M1/66

CPC classification number: G06F1/0321

Abstract: A cost effective waveform-generating apparatus that generates accurate and precise waveforms is disclosed. The present waveform-generating apparatus includes a memory for storing a sequence of sampled amplitudes of a waveform, said sampled amplitudes constituting at least two periods of said waveform; a counting circuit, electrically connected to the memory, responsive to a clock signal for generating counting signals; a controlling circuit, electrically connected to the memory and the counting circuit, responsive to the counting signals for controlling the memory to output the sampled amplitudes recurrently; and a digital to analog converter, electrically connected to the memory, for converting the recurrent sampled amplitudes into an analog output.

Abstract translation: 公开了一种产生精确和精确波形的成本有效的波形发生装置。 本波形生成装置包括：存储器，用于存储波形的采样振幅序列;所述采样振幅构成所述波形的至少两个周期; 计数电路，电连接到存储器，响应于用于产生计数信号的时钟信号; 控制电路，电连接到存储器和计数电路，响应于用于控制存储器的计数信号以循环地输出采样的幅度; 以及电连接到存储器的数模转换器，用于将复现的采样幅度转换为模拟输出。

公开(公告)号：US5688710A

公开(公告)日：1997-11-18

申请号：US757179

申请日：1996-11-27

Applicant: Bing-Yau Lu

Inventor： Bing-Yau Lu

IPC: H01L21/8238 ,  H01L27/00

CPC classification number: H01L21/823892 ,  Y10S148/007

Abstract: A method of fabricating a twin-well integrated circuit device to implant the dopants directly through the nitride layer including steps of: The pad oxide layer and nitride layer are formed on a P-type semiconductor silicon wafer. Then, the alignment mark photoresist pattern is formed by the conventional lithography technique, where the alignment mark region is in clear field, while other regions are in dark field. Next, the nitride layer is patterned by plasma-etching technique to form the nitride alignment mark. The N-well region is formed by lithography and ion-implantation techniques. Thereafter, the P-well region is formed by lithography and ion-implantation methods again. Next, the active device region photoresist is formed by lithography technique. The nitride layer is partially etched to open the windows by plasma-etching technique. The P-well region photoresist is then formed, followed by the deep-implantation process. The second P-well region photoresist is then formed, followed by the deep-implantation process. The field oxide regions for isolation are also grown in the window openings during the P-field drive-in step. Finally, the remaining of nitride layer is removed. This new process can reduce the number of processing steps so as to decrease the production cost.

Abstract translation: 一种制造双井集成电路器件的方法，用于直接通过氮化物层注入掺杂剂，包括以下步骤：衬垫氧化物层和氮化物层形成在P型半导体硅晶片上。 然后，通过常规光刻技术形成对准标记光致抗蚀剂图案，其中对准标记区域处于清晰的场，而其它区域处于暗场。 接下来，通过等离子体蚀刻技术对氮化物层进行图案化以形成氮化物对准标记。 N阱区域通过光刻和离子注入技术形成。 此后，再次通过光刻和离子注入方法形成P阱区。 接下来，通过光刻技术形成有源器件区域光致抗蚀剂。 部分蚀刻氮化物层以通过等离子体蚀刻技术打开窗口。 然后形成P阱区光致抗蚀剂，随后进行深注入工艺。 然后形成第二P阱区光致抗蚀剂，随后进行深度注入工艺。 用于隔离的场氧化物区域也在P场驱入步骤期间在窗口中生长。 最后，除去剩余的氮化物层。 这个新工艺可以减少加工步骤的数量，从而降低生产成本。

公开(公告)号：US5892394A

公开(公告)日：1999-04-06

申请号：US717069

申请日：1996-09-20

Applicant: Rong-Tyan Wu

Inventor： Rong-Tyan Wu

IPC: G05F3/24 ,  G05I3/02

CPC classification number: G05F3/247

Abstract: An intelligent bias voltage generating circuit capable of providing an electronic device with a reliable bias signal includes a power input terminal which is electrically connected to a power generating device for providing a power input, and a bias voltage generating circuit which is electrically connected to the power input terminal for responding to power fluctuations and generating a bias voltage signal output by a multi-section linear variation method.

Abstract translation: 能够为电子设备提供可靠的偏置信号的智能偏置电压发生电路包括电连接到用于提供电源输入的发电装置的电力输入端子和与电源电连接的偏置电压产生电路 输入端子，用于响应功率波动，并产生通过多段线性变化方法输出的偏置电压信号。

公开(公告)号：US5888904A

公开(公告)日：1999-03-30

申请号：US991083

申请日：1997-12-16

Applicant: Kuo-Chien Wu

Inventor： Kuo-Chien Wu

IPC: H01L21/027 ,  H01L21/3213 ,  H01L21/84 ,  H01L27/12 ,  H01L21/44

CPC classification number: H01L27/1203 ,  H01L21/0274 ,  H01L21/32139 ,  H01L21/84 ,  Y10S438/948 ,  Y10S438/949

Abstract: A method is provided for manufacturing a polysilicon with a relatively small line width. The method includes steps of: a) forming a first layer of photoresist with a line pattern having a first line interval and a first line width over the polysilicon; b) etching a portion of the polysilicon for forming the polysilicon with a second line interval x and a second line width y respectively equal to the first line interval and the first line width; c) forming a second layer of photoresist with a third line interval and a third line width over the polysilicon; d) etching another portion of the polysilicon for forming the polysilicon with a fourth line interval x`, equal to the third line interval, and a fourth line width y`; e) depositing a polysilicon film over the polysilicon with the relatively small line width; and f) etching a portion of the polysilicon film to form sidewalls of the polysilicon with the relatively small line width for adjusting the relatively small line width of the polysilicon.

Abstract translation: 提供了一种制造具有相对较小线宽的多晶硅的方法。 该方法包括以下步骤：a）在多晶硅上形成具有第一线间隔和第一线宽的线图案的第一光致抗蚀剂层; b）以分别等于第一线间隔和第一线宽的第二线间隔x和第二线宽y蚀刻用于形成多晶硅的部分多晶硅; c）在所述多晶硅上形成具有第三线间隔和第三线宽度的第二光致抗蚀剂层; d）蚀刻用于形成多晶硅的另一部分，其具有等于第三线间隔的第四线间隔x'和第四线宽y'; e）以相对小的线宽在多晶硅上沉积多晶硅膜; 以及f）蚀刻多晶硅膜的一部分以形成具有相对小的线宽的多晶硅的侧壁，用于调节多晶硅的相对小的线宽。

公开(公告)号：US5864502A

公开(公告)日：1999-01-26

申请号：US998679

申请日：1997-12-29

Applicant: Wu Shao-Yi ,  Wang Fu-Chung

Inventor： Wu Shao-Yi ,  Wang Fu-Chung

IPC: G11C7/06 ,  G11C16/26 ,  G11C16/06

CPC classification number: G11C16/26 ,  G11C7/067

Abstract: A sensing circuit for detecting data stored in a memory cell of an EEPROM by current detecting method is disclosed. The sensing circuit includes a constant current source supplying circuit for supplying a constant current. A loading circuit generates a current the same as the constant current generated by the current source supplying circuit when the memory cell sends out a logic low state signal, so that the data accessing speed during reading the data stored in the memory cell is increased.

Abstract translation: 公开了一种用于通过电流检测方法检测存储在EEPROM的存储单元中的数据的感测电路。 感测电路包括用于提供恒定电流的恒流源供应电路。 当存储器单元发出逻辑低电平状态信号时，加载电路产生与由电流源提供电路产生的恒定电流相同的电流，使得在读取存储在存储单元中的数据期间的数据访问速度增加。

公开(公告)号：US5818789A

公开(公告)日：1998-10-06

申请号：US541808

申请日：1995-10-10

Applicant: Wu Chi Yung ,  Kuo Chen Yu

Inventor： Wu Chi Yung ,  Kuo Chen Yu

IPC: G11C5/06 ,  G11C7/10 ,  G11C8/00 ,  G11C17/00

CPC classification number: G11C5/066 ,  G11C7/1018 ,  G11C8/00

Abstract: The present invention is related to an interface circuit for transmitting data corresponding to a specific address from/to a decoding memory unit, includes a bit-selection circuit pre-set therein a transmission mode, and a processing circuit electrically connected to the bit-selection circuit for transmitting the data according to the transmission mode. The present invention also relates to methods for reading out and writing in data corresponding to a specific address from/to a decoding memory unit.

Abstract translation: 本发明涉及一种用于从解码存储单元发送对应于特定地址的数据的接口电路，包括在其中预先设定了传输模式的比特选择电路，以及电连接到比特选择的处理电路 根据传输模式发送数据的电路。 本发明还涉及用于从与解码存储单元对应的特定地址读出数据的方法。