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1.发明申请Method for calculating call processing capacity of mobile communication system using internet communication network 失效利用互联网通信网络计算移动通信系统呼叫处理能力的方法公开(公告)号：US20010019959A1
公开(公告)日：2001-09-06
申请号：US09770352
申请日：2001-01-26
发明人： Hae Uk Choi
IPC分类号： H04Q007/20
CPC分类号： H04W24/00 , H04M3/36 , H04M7/12 , H04M2207/18
摘要： There is provided a method for calculating the call processing capacity of a mobile communication system using an Internet communication network. The present invention calculates and stores the call processing capacity of a mobile communication system using an Internet web browser and database to attain accurate call processing capacity information, thereby obtaining an optimal mobile communication system design. Furthermore, since multiple designers can share information about the calculated call processing capacity through a database, thereby making the call processing capacity information be actively effectively used.
摘要翻译： 提供了一种使用因特网通信网络来计算移动通信系统的呼叫处理能力的方法。 本发明使用因特网浏览器和数据库来计算和存储移动通信系统的呼叫处理能力，以获得准确的呼叫处理能力信息，从而获得最佳的移动通信系统设计。 此外，由于多个设计者可以通过数据库共享关于计算出的呼叫处理能力的信息，从而使得呼叫处理能力信息被有效地被有效地使用。
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公开(公告)号：US6151367A
公开(公告)日：2000-11-21
申请号：US63002
申请日：1998-04-20
申请人： Kwang-Woo Lim
发明人： Kwang-Woo Lim
IPC分类号： H03D3/00 , H03D7/16 , H03H17/02 , H03J7/04 , H03J7/06 , H04B1/26 , H04L27/02 , H04L27/06 , H04N5/455 , H04L27/22
摘要： A digital demodulator includes: a local oscillator for generating a predetermined frequency signal; a mixer for mixing an intermediate frequency (IF) signal with a local oscillation frequency signal output by the local oscillator; an A/D converter for converting a signal output by the mixer into a digital signal; an I and Q signal generator for producing I and Q signals from an output of the A/D converter; and a compensation unit for compensating the signals I and Q for phase errors.
摘要翻译： 数字解调器包括：本地振荡器，用于产生预定的频率信号; 用于将中频（IF）信号与由本地振荡器输出的本地振荡频率信号混合的混频器; A / D转换器，用于将由混频器输出的信号转换成数字信号; 用于从A / D转换器的输出产生I和Q信号的I和Q信号发生器; 以及补偿单元，用于补偿信号I和Q的相位误差。
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3.发明授权
公开(公告)号：US6094438A
公开(公告)日：2000-07-25
申请号：US950221
申请日：1997-10-14
申请人： Jin-Young Park , Hong-Koo Kang
发明人： Jin-Young Park , Hong-Koo Kang
CPC分类号： H04L1/0045 , H04L1/0063
摘要： The present invention discloses a parity detection device and method in a CDMA mobile communications system, which detects parity error in data output from a cell site modem (Q51601-2S1), and controls the data output when the parity error occurs, to improve the reliability in data communication. The invention converts serial data to be transmitted through a CSM into parallel data, checks if there is a parity error in the parallel data, and generates an interrupt when a parity error is detected. When the interrupt is generated, an output controller restrains the transmission of the serial data to be transmitted, which is outputted from the CSM, thereby preventing data having error from being transmitted.
摘要翻译： 本发明公开了一种CDMA移动通信系统中的奇偶校验检测装置和方法，其检测从小区现场调制解调器（Q51601-2S1）输出的数据中的奇偶校验错误，并且在奇偶校验错误发生时控制数据输出，以提高可靠性 在数据通信中。 本发明将要通过CSM发送的串行数据转换为并行数据，检查并行数据中是否存在奇偶校验错误，并在检测到奇偶校验错误时产生中断。 当产生中断时，输出控制器抑制从CSM输出的要发送的串行数据的发送，从而防止发送具有错误的数据。
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4.发明授权
公开(公告)号：US6005382A
公开(公告)日：1999-12-21
申请号：US9996
申请日：1998-01-21
申请人： Sang-Jin Lee
发明人： Sang-Jin Lee
CPC分类号： G01R23/02
摘要： An output signal measuring apparatus for a multiple frequency oscillator device and output signal measuring and correcting methods therefor which are capable of accurately and rapidly measuring a signal from each terminal of a multiple frequency oscillator device and minimizing a measuring and correcting time by automatically performing a correction required for a measurement. The apparatus is capable of measuring each terminal of a multiple frequency oscillator based on a switching circuit in accordance with control of a computer by integrating a plurality of measuring equipment into one system for satisfying a corresponding measuring item with respect to all terminals of the multiple frequency oscillator, automatically correcting with respect to each such terminal, and accurately and rapidly measuring each terminal of the multiple frequency oscillator by using a predetermined time and manpower, thus implementing mass production.
摘要翻译： 一种用于多频振荡器装置的输出信号测量装置及其输出信号测量和校正方法，其能够准确且快速地测量来自多频振荡器装置的每个端子的信号，并通过自动执行校正来最小化测量和校正时间 测量所需。 该装置能够根据计算机的控制，通过将多个测量设备集成到一个系统中来满足相对于多频率的所有终端的相应测量项目，基于切换电路来测量多频振荡器的每个终端 振荡器，相对于每个这样的终端自动校正，并且通过使用预定的时间和人力精确和快速地测量多频率振荡器的每个终端，从而实现批量生产。
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5.发明授权
公开(公告)号：US5959703A
公开(公告)日：1999-09-28
申请号：US902141
申请日：1997-07-30
申请人： Dae-Il Oh , Eung-Ryeol Kim , Dae-Hyun Kim , Won-Jin Lee
发明人： Dae-Il Oh , Eung-Ryeol Kim , Dae-Hyun Kim , Won-Jin Lee
CPC分类号： H04N21/2383 , H04N19/89 , H04N21/4382
摘要： In an error data removing apparatus and method by decoding delay in a DTV system which employs a decoder of the VSB standard, respective segments or respective fields are divided into area 1 and area 2 using a starting point of decoded data as a reference to provide the decoded data of said area 1 section without involving delay and provide the decoded data of said area 2 section by delaying as long as a sync signal. A memory is utilized as the decoded data delay apparatus, and at this time, a value of a counter used for generating an address for reading/writing of the memory is utilized to delay the segment sync signal and field sync signal as required without separately using flip-flop or memory.
摘要翻译： 在采用VSB标准的解码器的DTV系统中解码延迟的误差数据去除装置和方法中，使用解码数据的起始点将各个段或各个区域划分为区域1和区域2作为参考，以提供 所述区域1部分的解码数据而不涉及延迟，并且通过延迟长达同步信号来提供所述区域2部分的解码数据。 使用存储器作为解码数据延迟装置，此时，用于产生用于存储器的读/写的地址的计数器的值被用来根据需要延迟段同步信号和场同步信号，而不需要单独使用 触发器或内存。
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6.发明授权
公开(公告)号：US5877877A
公开(公告)日：1999-03-02
申请号：US663750
申请日：1996-06-14
申请人： Jae-Hyung Park
发明人： Jae-Hyung Park
IPC分类号： G06F11/20 , G06F13/00 , H04H1/02 , H04H20/69 , H04N7/10 , H04N7/16 , H04N7/22 , H04N17/00 , H04N21/61 , H04N21/647 , H04B10/08
CPC分类号： H04H20/69 , H04B10/0799 , H04N17/00
摘要： An apparatus for remedying errors in a head end monitoring block includes an optical transmitting section for transmitting/receiving aerial broadcasting signals and its own broadcasting signals; a host computer for controlling respective sections of a head end; a master control section for monitoring an operating state of a transmitting path of the head end and the codeck boards; a master mother section for receiving certain signals from the master control section so as to connect communication paths between the optical transmitting section, the host computer and the master control section; a slave control section for monitoring the transmission state of a relevant codeck board, and for receiving an error occurrence signal from the master control section so as to carry out the function of the master control section in place of it; and a slave mother section for receiving an error occurrence signal from the master control section so as to connect communication paths between the optical transmitting section, the host computer and the master control section. In operation, if an error occurs in the master control board, the slave control board takes over the function of the master control board to carry out the head end block monitoring task in place of it. A method for remedying errors in a head end monitoring block includes analogous steps.
摘要翻译： 用于补救前端监视块中的错误的装置包括：用于发送/接收空中广播信号的光发送部分及其自己的广播信号; 主机，用于控制头端的各个部分; 主控制部，用于监视头端和码板的发送路径的动作状态; 主母部分，用于从主控部分接收某些信号，以连接光传输部分，主计算机和主控部分之间的通信路径; 从控制部分，用于监视相关的代码板的传输状态，并且从主控部分接收错误发生信号，以便执行主控部分的功能代替它; 以及从母机部分，用于从主控部分接收错误发生信号，以便连接光发射部分，主计算机和主控制部分之间的通信路径。 在操作中，如果主控板发生错误，则从控制板接管主控板的功能，执行头端块监控任务代替主控板。 用于补救前端监视块中的错误的方法包括类似的步骤。
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公开(公告)号：US5854816A
公开(公告)日：1998-12-29
申请号：US950035
申请日：1997-10-14
申请人： Si-Deog Kim , Hyun-Woo Ha
发明人： Si-Deog Kim , Hyun-Woo Ha
CPC分类号： H04L12/2697 , H04J3/0685 , H04L43/50 , H04J3/14 , H04J3/1623
摘要： A loop back device of a packet communication T1 network includes: a clock generating part which inputs a frame divisional clock and a reference clock, inserts a modulated clock at a predetermined position of the reference clock to generate a main clock and is synchronous to the transformed clock position to generate a system clock for generating and extracting loop back data; a loop back data inserting part which generates the loop back data and is synchronous to the system clock generated from the clock generating part to insert the loop back data into transmission data; a framer and interface part which inputs the transmission data including the loop back data outputted from the loop back data inserting part to transmit the input data to the T1 network and receives is data from the T1 network; a loop back data extracting part which is synchronous to the system clock generated in the clock generating part to extract the loop back data from reception data outputted from the framer and interface part; and a processor which outputs the transmission data to the loop back data inserting part and inputs said loop back data extracted from said loop back data extracting part, to output network testing data.
摘要翻译： 分组通信T1网络的环回装置包括：时钟产生部分，其输入帧分时钟和参考时钟，将调制时钟插入参考时钟的预定位置，以产生主时钟，并与转换后的 时钟位置以产生用于生成和提取循环数据的系统时钟; 环回数据插入部，其生成回送数据，并且与从时钟生成部生成的系统时钟同步，将回送数据插入到发送数据中; 输入包括从环回数据插入部输出的环回数据的发送数据的成帧器和接口部，将输入的数据发送到T1网络并接收来自T1网络的数据; 与在时钟生成部中生成的系统时钟同步的环回数据提取部，从成帧器和接口部输出的接收数据中提取回送数据; 以及处理器，其将所述发送数据输出到所述环回数据插入部，并输入从所述环回数据提取部提取的所述环回数据，以输出网络测试数据。
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公开(公告)号：US5799019A
公开(公告)日：1998-08-25
申请号：US664001
申请日：1996-06-14
申请人： Young-Goo Kim , Sung-Dong Kim
发明人： Young-Goo Kim , Sung-Dong Kim
CPC分类号： H04J3/1635
摘要： A circuit for converting frame data is disclosed, in which data communications can be carried out by matching the T1 repeater line of the North American method and the E1 repeater line of the CEPT. The four 32-channel frame data of the E1 line of the CEPT method are converted into parallel data of 8-bit one channel, and are stored into four 64-byte buffers. The stored 32-channel frame data are read out by 24 channels at a time, while the remaining data of the 6 channels are added to the data which have been stored in the buffers. Thus five 24-channel frame data are converted into serial data before being outputted. Of the five 24-channel frame data of the T1 repeater line of the North American method, four 24-channel frame data are stored into four 64-byte buffers, while the remaining one 24-channel frame data are separated by 6 so as to store them into the four 64-byte buffers, so that the four 64-byte buffers can store the 32-channel data respectively. The 32-channel data which have been stored in the four 64-byte buffers are sequentially read out, and then, are converted into serial data before outputting them.
摘要翻译： 公开了一种用于转换帧数据的电路，其中可以通过匹配北美方法的T1中继线和CEPT的E1中继线来进行数据通信。 CEPT方法E1线的四个32通道帧数据转换为8位一个通道的并行数据，并存储在四个64字节缓冲区中。 所存储的32通道帧数据一次被24个通道读出，而6个通道的剩余数据被添加到已经存储在缓冲器中的数据。 因此，在输出之前，将五个24通道帧数据转换为串行数据。 在北美方法的T1中继线的五个24信道帧数据中，四个24信道帧数据被存储到四个64字节缓冲器中，而剩下的一个24信道帧数据被分离为6，以便 将它们存储到四个64字节缓冲区中，以便四个64字节缓冲区可以分别存储32个通道数据。 已经存储在四个64字节缓冲器中的32通道数据被顺序地读出，然后在输出之前转换成串行数据。
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公开(公告)号：US5530812A
公开(公告)日：1996-06-25
申请号：US246057
申请日：1994-05-19
申请人： You Seong Kim , Sang Rae Lee
发明人： You Seong Kim , Sang Rae Lee
CPC分类号： G06F13/4213
摘要： A bus interface circuit is for coupling between a microprocessor having an architecture in which address and data buses are separated and peripheral equipment having a multiplexing bus architecture. The bus interface circuit includes a first delay circuit for delaying a first address strobe signal of a microprocessor to obtain a first data strobe signal, a second delay circuit for delaying the first data strobe signal to obtain a second data strobe signal for the peripheral equipment, a logic circuit for multiplying an inverted first data strobe signal and the first address strobe signal to obtain a second address strobe signal for the peripheral equipment, a first buffer enabled by the first data strobe signal for transmitting address data of the microprocessor, and second buffer means enabled by the second address strobe signal for transmitting and receiving data information between the microprocessor and the peripheral equipment.
摘要翻译： 总线接口电路用于在具有地址和数据总线分离的架构的微处理器之间耦合以及具有复用总线结构的外围设备。 总线接口电路包括用于延迟微处理器的第一地址选通信号以获得第一数据选通信号的第一延迟电路，用于延迟第一数据选通信号以获得外围设备的第二数据选通信号的第二延迟电路， 逻辑电路，用于将反相的第一数据选通信号和第一地址选通信号相乘以获得用于外围设备的第二地址选通信号，由第一数据选通信号用于发送微处理器的地址数据的第一缓冲器和第二缓冲器 由第二地址选通信号启用的装置，用于在微处理器和外围设备之间发送和接收数据信息。
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公开(公告)号：US5145137A
公开(公告)日：1992-09-08
申请号：US619004
申请日：1990-11-28
申请人： Heung M. Choi
发明人： Heung M. Choi
CPC分类号： G02F1/133308 , H04B1/08
摘要： A movable display assembly is incorporated in the car stereo for adjusting the screen viewing angle of the LCD. The movable display assembly comprises a semi-spherical display means and a guide shaft for guiding the display means in any direction within a semi-circular cavity which is formed in the forwardly opening of the front panel of the car stereo. The semi-spherical display means includes a convex rear wall and an LCD constituting the front face of the display means. The guide shaft extends horizontally from the rear face of the display means and is loosely fitted in an opening formed in the cavity. A frictional means is provided in order to hold the movable display means in place.
摘要翻译： 可移动显示组件被并入汽车立体声用于调节LCD的屏幕视角。 可移动显示组件包括半球形显示装置和引导轴，用于在形成在汽车立体声前面板的向前开口中的半圆形空腔内的任何方向上引导显示装置。 半球形显示装置包括构成显示装置前表面的凸形后壁和LCD。 引导轴从显示装置的后表面水平延伸，并且松动地装配在形成在空腔中的开口中。 提供摩擦装置以便将可移动显示装置保持就位。
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