公开(公告)号：US5111324A

公开(公告)日：1992-05-05

申请号：US535744

申请日：1990-06-08

Applicant: Fazlollah R. Jahromi

Inventor： Fazlollah R. Jahromi

IPC: H04B10/04 ,  H03F3/08 ,  H04B1/06 ,  H04B10/06 ,  H04B10/14 ,  H04B10/158 ,  H04B10/26 ,  H04B10/28

CPC classification number: H03F3/087 ,  H04B10/6911

Abstract: An optical receiver incorporating a voltage dependant impedance arranged to shunt excess AC photodetector signal away from the receiver amplifier in response to light level.

公开(公告)号：US5100260A

公开(公告)日：1992-03-31

申请号：US625961

申请日：1990-12-11

Applicant: Brian T. Knight

Inventor： Brian T. Knight

IPC: H02G1/10

CPC classification number: H02G1/10

Abstract: A cable burying device (3) comprises several heavy hollow tapered elements (7, 8) coupled to each other (7A, 7B, 8A, 8B) to provide limited flexibility, which is towed along the seabed and which digs a trench, the cable (1) passing through the length of the device to become buried in the trench. A guide tube (2) to guide the cable (1) from the ship to the burying device (3) has a flexible lattice construction (FIGS. 6, 7, 8) which can be folded flat for ease of storage on the ship.

Abstract translation: 电缆埋入装置（3）包括彼此耦合的多个重的中空锥形元件（7,8）（7A，7B，8A，8B），以提供有限的柔性，其沿着海床被牵引并且挖掘沟槽，电缆 （1）穿过设备的长度以埋在沟槽中。 将电缆（1）从船舶引导到掩埋装置（3）的引导管（2）具有柔性的格子结构（图6，图7，图8），其可以被折叠成平坦的，以便于存储在船上。

公开(公告)号：US5047757A

公开(公告)日：1991-09-10

申请号：US239994

申请日：1988-09-02

Applicant: Matthew F. Bone ,  Ian Coulson ,  Johnathan R. Hughes ,  Peter W. Ross ,  Frances C. Saunders ,  Paul W. H. Surguy

Inventor： Matthew F. Bone ,  Ian Coulson ,  Johnathan R. Hughes ,  Peter W. Ross ,  Frances C. Saunders ,  Paul W. H. Surguy

IPC: G02F1/133 ,  G09G3/36

CPC classification number: G09G3/3629 ,  G09G2310/06

Abstract: A method is disclosed for addressing a matrix-array type liquid crystal layer. The cell has a plurality of pixels which are defined by regions of overlap between two sets of electrodes which sandwich a liquid crystal layer, each pixel having two states. The response time for switching between the two states is dependent upon the voltage across the liquid crystal layer, with a minimum occurring at a particular voltage. The method includes applying a strobe waveform to a selected member of a first set of the electrodes while a data waveform is applied to each member of the second set of electrodes. A waveform for switching a pixel defined by the selected member comprises a switching pulse of a given voltage magnitude and given duration. A waveform for not switching a pixel defined by the selected member comprises a non-switching pulse of a voltage magnitude greater than the given voltage magnitude of the switching pulse and a duration less than the given duration of the switching pulse.

公开(公告)号：US5028931A

公开(公告)日：1991-07-02

申请号：US528596

申请日：1990-05-24

Applicant: Christopher R. Ward

Inventor： Christopher R. Ward

IPC: G01S7/28 ,  G01S7/36 ,  H01Q3/26

CPC classification number: H01Q3/2605 ,  G01S7/2813 ,  G01S7/36

Abstract: An off-line processor arrangement for a broadband accelerated convergence adaptive antenna array wherein signals from a plurality of antenna elements are applied to respective identical tapped delay lines (T) the outputs of which are fed through individual signal weighting means to a beamforming network (BFN), the arrangement including one or more lattice filter means (LF) to which the auxiliary antenna element signals are applied together with the output response of the beamforming network to compute sets of weight correction vectors (* W) with which to update weight coefficients and means for storing said updated coefficients, said stored coefficients being applied to the individual signal weighting means to weight the outputs of the tapped delay lines.

Abstract translation: 一种用于宽带加速会聚自适应天线阵列的离线处理器装置，其中来自多个天线元件的信号被施加到各自相同的抽头延迟线（T），其输出通过各个信号加权装置馈送到波束形成网络（BFN ），所述布置包括一个或多个格子滤波器装置（LF），辅助天线单元信号与波束形成网络的输出响应一起施加到其上，以计算用于更新加权系数的权重校正向量（* W） 用于存储所述更新的系数的装置，所述存储的系数被应用于各个信号加权装置以加权所抽头延迟线的输出。

公开(公告)号：US5024503A

公开(公告)日：1991-06-18

申请号：US479119

申请日：1990-02-13

Applicant: Duncan A. Gunn ,  Stephen J. McManus

Inventor： Duncan A. Gunn ,  Stephen J. McManus

IPC: F16L5/02 ,  G02B6/00 ,  G02B6/24 ,  G02B6/42 ,  G02B6/44

CPC classification number: G02B6/4428 ,  G02B6/4248

Abstract: An optical fibre gland for a submerged repeater comprising an insulating body (1) having a bore (4) accommodating a pressure tube (5). A high pressure end fitting (8) is secured to the tube and the body and a low pressure end fitting (12) is secured only to the tube. The tube and fibres are water and gas blocked and the construction is such as to enable the gland to operate satisfactorily over a wide temperature range.

Abstract translation: 一种用于浸没式中继器的光纤密封套，包括具有容纳压力管（5）的孔（4）的绝缘体（1）。 高压端配件（8）固定到管和主体上，低压端配件（12）仅固定在管上。 管和纤维是水和气体阻塞的，并且结构是使得压盖能够在宽的温度范围内令人满意地运行。

公开(公告)号：US5007703A

公开(公告)日：1991-04-16

申请号：US454184

申请日：1989-12-21

Applicant: Peter G. Hale ,  John N. Russell

Inventor： Peter G. Hale ,  John N. Russell

IPC: B29C39/18 ,  B29D11/00 ,  G02B6/44

CPC classification number: G02B6/4483 ,  B29C39/18 ,  B29D11/00663 ,  G02B6/4427 ,  G02B6/4479 ,  B29L2011/0075

Abstract: A one-shot method of making an optical fiber package (FIG. 1) for a submarine cable. A plurality of fibers (1) are fed into a space delimited by one or more elongate elements from which a tubular structure (3) can be formed, for example a C-section. A liquid filling material, such as a two-part exothermic curing polyurethne, mixed by static mixer (16), is injected into the C-section which is then closed by a die (17). The filling material rapidly cures to a resilient solid (2) in which the fibers are embedded before hauler (18) is reached. The fibers are spaced apart from one another and the tubular structure by means including a guide structure (14,15) as they enter the C-section and this is maintained in the cured material.

Abstract translation: 制造海底电缆的光纤封装（图1）的一次性方法。 多个纤维（1）被供给到由一个或多个细长元件限定的空间中，可以形成管状结构（3），例如C形截面。 将通过静态混合器（16）混合的液体填充材料（例如两部分放热固化聚氨酯）注入到C部分中，然后由模具（17）封闭。 填充材料快速固化成弹性固体（2），其中在到达运输工具（18）之前嵌入纤维。 所述纤维彼此间隔开，并且所述管状结构通过包括引导结构（14,15）的装置进入所述C形部分并且将其保持在所述固化材料中。

公开(公告)号：US4992654A

公开(公告)日：1991-02-12

申请号：US227014

申请日：1988-08-01

Applicant: William A. Crossland ,  Neil Collings

Inventor： William A. Crossland ,  Neil Collings

IPC: G02F1/13 ,  G02F3/00 ,  G02F3/02

CPC classification number: G02F3/022

Abstract: An optical logic device consists of a bistable liquid crystal layer (BOD 1) of the thermally-induced birefringent (TIB) type settable by one or more write beams and rfead by a beam of a different wavelength or different light polarization. Thus the read and write beams are optically decoupled. Two such devices (BOD 1 and BOD 2) in tandem form a 3-input AND gate. Here beams A and B are write beams for the first device, (BOD 1), and beam C is the read beam for the first device. For the second device (BOD 2) the write beams are the output of the first device (BOD 1) and beam D, the read beam being beam E. The two read beams have different wavelengths from the write beam. In a second version, the liquid crystal layer is on the base of a prism via which the beams reads it. Write beams go right through the layer, while a read beam is "reflected" from the layer but is modulated by the state thereof. This is an OR gate. Logic assemblies can use combinations of such AND or OR gates.

公开(公告)号：US4965216A

公开(公告)日：1990-10-23

申请号：US471031

申请日：1990-01-26

Applicant: Peter D. Scovell ,  Peter F. Blomley ,  Roger L. Baker

Inventor： Peter D. Scovell ,  Peter F. Blomley ,  Roger L. Baker

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/08

CPC classification number: H01L29/66272 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/0804 ,  Y10S148/123 ,  Y10S148/124

Abstract: A process for fabricating a CMOS compatible bipolar transistor is described. The transistor, which is of the polysilicon emitter type, is fabricated by forming a p-type layer in a well, providing a polysilicon emitter in contact with the layer, using the emitter as a mask to implant p.sup.+ -type base contact regions, and applying contacts to the device.

Abstract translation: 描述了制造CMOS兼容双极晶体管的工艺。 多晶硅发射体类型的晶体管通过在阱中形成p型层来制造，提供与该层接触的多晶硅发射极，使用发射极作为掩模来注入p +型基极接触区域，以及 将联系人应用到设备。

公开(公告)号：US4950045A

公开(公告)日：1990-08-21

申请号：US377468

申请日：1989-07-10

Applicant: Terry Bricheno ,  Alan Fielding ,  Stephen Day

Inventor： Terry Bricheno ,  Alan Fielding ,  Stephen Day

IPC: G02B6/28

CPC classification number: G02B6/2813

Abstract: A 1.times.N single mode optical waveguide coupler comprises a single input optical fibre (1), a slab-like mixer waveguide (3) and a plurality (N) of output optical fibres (2). As a result of interference effects light introduced into the mixer waveguide (3) via the centrally located input fibre (1) produces a linear array of output spots at various intervals along the length of the mixer waveguide. The length of the mixer waveguide is chosen such that the output optical fibres are aligned with one such array of output spots. The fibres may be adiabatically tapered to a smaller diameter in order to increase their modal spot size.

Abstract translation: 1xN单模光波导耦合器包括单输入光纤（1），板状混合波导（3）和多（N）个输出光纤（2）。 作为干扰效应的结果，通过中心位置的输入光纤（1）引入混合器波导（3）的光线沿着混频器波导的长度产生沿不同间隔的输出光点的线性阵列。 选择混频器波导的长度，使得输出光纤与一个这样的输出点阵列对齐。 纤维可以绝热地锥形成较小的直径以增加其模态斑点尺寸。

公开(公告)号：US4914048A

公开(公告)日：1990-04-03

申请号：US133269

申请日：1987-12-16

Applicant: Peter D. Scovell ,  Peter F. Blomley ,  Roger L. Baker

Inventor： Peter D. Scovell ,  Peter F. Blomley ,  Roger L. Baker

IPC: H01L27/092 ,  H01L21/331 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/088 ,  H01L29/73 ,  H01L29/732

CPC classification number: H01L21/8249 ,  H01L21/8238 ,  H01L27/0623 ,  Y10S148/01

Abstract: A bipolar transistor structure (1) which can be used in an integrated circuit where bipolar (1) and CMOS transistors (2,3) are formed simultaneously on one substrate. In integrated circuit form the material, for example polycrystalline silicon, used for the gates (11,21) of the CMOS transistors is also used for the emitters (29) of the bipolar transistors, the collectors of the bipolar devices are comprised by doped wells (5) in the substrate (4) and the base contacts of the bipolar devices are comprised by regions (27,27a) equivalent to source and drain regions (17,18) of the n-well MOS transistors and bridged by base implants (28). The conventional CMOS processing is modified by the addition of two masking steps and one implant (base implant). One masking step defines the area for the base implant (18) and the other masking step defines an area of the oxide (30) over the base implant which must be removed to allow contact between the polycrystalline silicon (29), which is suitably doped to provide the emitter, and the base ( 27,27a,28). The base contacts are produced in a semi-self-aligned manner.