公开(公告)号：US08476143B2

公开(公告)日：2013-07-02

申请号：US13349416

申请日：2012-01-12

Applicant: Pietro Montanini ,  Marta Mottura ,  Giuseppe Croce

Inventor： Pietro Montanini ,  Marta Mottura ,  Giuseppe Croce

IPC: H01L21/76

CPC classification number: H01L29/10 ,  H01L21/26586 ,  H01L21/743 ,  H01L29/1087 ,  H01L29/423 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An embodiment of an integrated circuit includes first and second semiconductor layers and a contact region disposed in the second layer. The first semiconductor layer is of a first conductivity, and the second semiconductor layer is disposed over the first layer and has a surface. The contact region is contiguous with the surface, contacts the first layer, includes a first inner conductive portion, and includes an outer conductive portion of the first conductivity. The contact region may extend deeper than conventional contact regions, because where the inner conductive portion is formed from a trench, doping the outer conductive portion via the trench may allow one to implant the dopants more deeply than conventional techniques allow.

Abstract translation: 集成电路的实施例包括第一和第二半导体层以及设置在第二层中的接触区域。 第一半导体层具有第一导电性，第二半导体层设置在第一层上并具有表面。 接触区域与表面邻接，接触第一层，包括第一内部导电部分，并且包括第一导电性的外部导电部分。 接触区域可以比常规接触区域更深，因为在内部导电部分由沟槽形成的情况下，通过沟槽掺杂外部导电部分可以使其比常规技术允许的更深入地注入掺杂剂。

公开(公告)号：US20070109866A1

公开(公告)日：2007-05-17

申请号：US11539708

申请日：2006-10-09

Applicant: Kuhong Jeong ,  Hyungsang Lee ,  Jacopo Mulatti

Inventor： Kuhong Jeong ,  Hyungsang Lee ,  Jacopo Mulatti

IPC: G11C11/34

CPC classification number: G11C16/3459 ,  G11C16/3454 ,  G11C29/832 ,  G11C2216/14

Abstract: A method of programming cells in a nonvolatile memory is based upon a Global Verify operation and a Byte-by-byte Verify operation. The cells of a destination page of the nonvolatile memory are programmed, and logic values stored in the programmed cells of a source page of the same memory are verified that they have been correctly copied into corresponding cells of the destination page. The method carries out the fast but inadequate-at-times Global Verify operation, and if the Global Verify operation fails for a certain number of attempts, the Byte-by-byte Verify operation is carried out, which is slower but accurate.

Abstract translation: 在非易失性存储器中编程单元的方法是基于全局验证操作和逐字节验证操作。 非易失性存储器的目的地页面的单元被编程，并且存储在相同存储器的源页面的编程单元中的逻辑值被证实已被正确复制到目的地页面的相应单元中。 该方法执行快速但不足的全局验证操作，并且如果全局验证操作在一定次数的尝试中失败，则会执行逐字节验证操作，这是较慢但准确的。

公开(公告)号：US09502961B2

公开(公告)日：2016-11-22

申请号：US14734680

申请日：2015-06-09

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Claudia Castelli

IPC: G05F1/61 ,  H02M1/42 ,  H02M1/00

CPC classification number: H02M1/4208 ,  G05F1/61 ,  H02M1/4225 ,  H02M2001/0054 ,  Y02B70/126 ,  Y02B70/1491

Abstract: A control circuit controls a switching power factor corrector based on switch off-time modulation by controlling the input electric charge during on-time. The circuit includes a charge current generator that generates charge current as a replica of a current sense signal amplified with a gain corresponding to the square of peak value of a rectified input voltage, a loop capacitor charged with the charge current during on-time intervals and discharged with a discharge current during off-time intervals, a discharge current generator that generates the discharge current proportional to a product of a comparison voltage and a difference between a regulated output voltage and the rectified input voltage, and a PWM modulator that senses a charge voltage of the loop capacitor, turns on the switch for an on-time duration in response to detecting that the charge voltage nullifies, and turns off the switch when the on-time duration has elapsed.

Abstract translation: 控制电路通过在接通时间期间控制输入电荷来控制基于开关关断时间调制的开关功率因数校正器。 该电路包括充电电流发生器，其产生作为电流感测信号的复制品的电流，该电流感测信号以对应于整流输入电压的峰值平方的放大倍数，在接通时间间隔期间充满充电电流的环路电容器，以及 在关断时间间隔内以放电电流放电，放电电流产生器，其产生与比较电压和调节输出电压与整流输入电压之间的差成比例的放电电流;以及PWM调制器，其感测电荷 回路电容器的电压响应于检测到充电电压无效而导通开关导通时间，并且在接通时间已经过去时关断开关。

公开(公告)号：US10453833B2

公开(公告)日：2019-10-22

申请号：US15839501

申请日：2017-12-12

Applicant: STMicroelectronics S.r.l.

Inventor： Alberto Pagani

IPC: H01L23/498 ,  H01L25/065 ,  H01L21/56 ,  H05K1/18 ,  H01L27/02 ,  H01L21/768 ,  H01L23/31 ,  H01L23/48 ,  H01L23/66 ,  H01L23/00 ,  H01L21/683 ,  H01L25/10 ,  H01L21/66

Abstract: An electronic system supports superior coupling by implementing a communication mechanism that provides at least for horizontal communication for example, on the basis of wired and/or wireless communication channels, in the system. Hence, by enhancing vertical and horizontal communication capabilities in the electronic system, a reduced overall size may be achieved, while nevertheless reducing complexity in printed circuit boards coupled to the electronic system. In this manner, overall manufacturing costs and reliability of complex electronic systems may be enhanced.

公开(公告)号：US20080285745A1

公开(公告)日：2008-11-20

申请号：US11547195

申请日：2004-03-29

Applicant: Yannick Teglia ,  Fabrice Romain ,  Pierre-Yvan Liardet ,  Pasqualina Fragneto ,  Fabio Sozzani ,  Guido Bertoni

Inventor： Yannick Teglia ,  Fabrice Romain ,  Pierre-Yvan Liardet ,  Pasqualina Fragneto ,  Fabio Sozzani ,  Guido Bertoni

IPC: H04L9/06

CPC classification number: H04L9/0631 ,  H04L9/003 ,  H04L2209/046 ,  H04L2209/08 ,  H04L2209/122

Abstract: A processor for executing a Rijndeal algorithm which applies a plurality of encryption rounds to a data block array in order to obtain an array of identical size, each round involving a key block array and a data block substitution table, wherein said processor comprises: a first input register (102) containing an input data block column; an output register (111) containing an output data block column or an intermediate block column; a second input register (101) containing a key block column or the intermediate data blocks; a block substitution element (104) receiving the data one block at a time following the selection (103) thereof in the first register and providing, for each block, a column of blocks; an element (109) applying a cyclic permutation to the substitution circuit column blocks; and an Exclusive-OR combination element (110) combining the permutation circuit column blocks with the content of the second register, the result of said combination being loaded into the output register.

Abstract translation: 一种用于执行Rijndeal算法的处理器，该Rijndeal算法将多个加密回合应用于数据块阵列，以便获得相同大小的阵列，每轮涉及密钥块阵列和数据块替换表，其中所述处理器包括：第一 输入寄存器（102），其包含输入数据块列; 包含输出数据块列或中间块列的输出寄存器（111）; 包含密钥块列或中间数据块的第二输入寄存器（101）; 块替换元件（104）在第一寄存器中的选择（103）之后的时间接收数据一个块，并为每个块提供一列块; 向替代电路列块施加循环置换的元件（109）; 以及将置换电路列块与第二寄存器的内容组合的异或组合元件（110），所述组合的结果被加载到输出寄存器中。

公开(公告)号：US09111895B2

公开(公告)日：2015-08-18

申请号：US13579562

申请日：2011-02-16

Applicant: Alberto Pagani

Inventor： Alberto Pagani

IPC: G01R31/02 ,  H01L21/66 ,  H01L21/768

CPC classification number: G01R31/275 ,  G01R31/2853 ,  H01L21/76898 ,  H01L22/34 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An embodiment of a testing system for carrying out electrical testing of at least one first through via extending, at least in part, through a substrate of a first body of semiconductor material. The testing system has a first electrical test circuit integrated in the first body and electrically coupled to the first through via and to electrical-connection elements carried by the first body for electrical connection towards the outside; the first electrical test circuit enables detection of at least one electrical parameter of the first through via through the electrical-connection elements.

Abstract translation: 用于进行至少一个第一通孔的电测试的测试系统的实施例，所述至少一个第一通孔至少部分地延伸穿过第一半导体材料体的衬底。 测试系统具有集成在第一主体中并与第一通孔电耦合的第一电测试电路和由第一主体携带的电连接元件，用于电连接到外部; 第一电测试电路使得能够通过电连接元件检测第一通孔的至少一个电参数。

公开(公告)号：US07569492B1

公开(公告)日：2009-08-04

申请号：US12111095

申请日：2008-04-28

Applicant: David L. Chen ,  Yuh-Jia Su ,  Eddie Ka Ho Chiu ,  Maria Paola Pozzoli ,  Senzi Li ,  Giuseppe Colangelo ,  Simone Alba ,  Simona Petroni

Inventor： David L. Chen ,  Yuh-Jia Su ,  Eddie Ka Ho Chiu ,  Maria Paola Pozzoli ,  Senzi Li ,  Giuseppe Colangelo ,  Simone Alba ,  Simona Petroni

IPC: H01L21/302

CPC classification number: B08B7/0035 ,  H01J2237/335 ,  H01L21/02063 ,  H01L21/02071

Abstract: The current invention provides methods for performing a cleaning process that provides greater cleaning efficiency with less damage to device structures. After etching and photoresist stripping, a first plasma clean is performed. The first plasma clean may comprise one or more steps. Following the first plasma clean, a first HO based clean is performed. The first HO based clean may be a de-ionized water rinse, a water vapor clean, or a plasma clean, where the plasma includes hydrogen and oxygen. Following the first HO based clean, a second plasma clean is performed, which may comprise one or more steps. A second HO based clean follows the second plasma clean, and may be a de-ionized water rinse, a water vapor clean, or a plasma clean, where the plasma includes hydrogen and oxygen. For plasma processes, an RF generated plasma, a microwave generated plasma, an inductively coupled plasma, or combination may be used. Embodiments of the invention are performed after an etch, such as a metal etch, via etch, contact etch, polysilicon etch, nitride etch or shallow trench isolation etch has been performed. Photoresist may be removed either prior to, during, or after cleaning processes according to embodiments of the invention, using an oxygen-containing plasma. Photoresist removal may be performed at low temperatures.

Abstract translation: 本发明提供了用于执行清洁过程的方法，其提供更高的清洁效率，同时对设备结构的损坏较小。 在蚀刻和光致抗蚀剂剥离之后，进行第一等离子体清洁。 第一等离子体清洁可以包括一个或多个步骤。 在第一次等离子体清洁之后，执行第一次基于HO的清洁。 第一个基于HO的清洁可以是去离子水冲洗，水蒸气清洁或等离子体清洁，其中等离子体包括氢和氧。 在第一个基于HO的清洁之后，执行第二等离子体清洁，其可以包括一个或多个步骤。 第二个基于HO的清洁遵循第二等离子体清洁，并且可以是去离子水冲洗，水蒸汽清洁或等离子体清洁，其中等离子体包括氢和氧。 对于等离子体处理，可以使用RF产生的等离子体，微波产生的等离子体，电感耦合等离子体或组合。 通过蚀刻，接触蚀刻，多晶硅蚀刻，氮化物蚀刻或浅沟槽隔离蚀刻等蚀刻，例如金属蚀刻，进行本发明的实施例。 可以使用含氧等离子体在根据本发明的实施方案的清洁方法之前，期间或之后除去光致抗蚀剂。 可以在低温下进行光刻胶去除。

公开(公告)号：US07078294B2

公开(公告)日：2006-07-18

申请号：US10971774

申请日：2004-10-22

Applicant: Emilio Camerlenghi ,  Alfonso Maurelli ,  Daniela Peschiaroli ,  Paola Zabberoni

Inventor： Emilio Camerlenghi ,  Alfonso Maurelli ,  Daniela Peschiaroli ,  Paola Zabberoni

IPC: H01L21/336

CPC classification number: H01L27/11526 ,  H01L21/823468 ,  H01L23/3192 ,  H01L27/105 ,  H01L27/11536 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for sealing electronic devices formed on a semiconductor substrate includes forming at least one first conductive layer on a first portion of the semiconductor substrate for defining electronic devices, and forming a second conductive layer on a second portion of semiconductor substrate for also defining electronic devices. First regions are formed in the at least one first conductive layer for defining electronic devices, and a first sealing layer is formed on the whole semiconductor substrate to seal the first regions. Second regions are formed in the second conductive layer for defining electronic devices, and a second sealing layer is formed on the whole semiconductor substrate to seal the second regions.

Abstract translation: 用于密封形成在半导体衬底上的电子器件的方法包括在半导体衬底的用于限定电子器件的第一部分上形成至少一个第一导电层，以及在半导体衬底的第二部分上形成第二导电层，用于还限定电子器件 。 第一区域形成在用于限定电子器件的至少一个第一导电层中，并且在整个半导体衬底上形成第一密封层以密封第一区域。 第二区域形成在用于限定电子器件的第二导电层中，并且在整个半导体衬底上形成第二密封层以密封第二区域。