公开(公告)号：US20210257456A1

公开(公告)日：2021-08-19

申请号：US17307749

申请日：2021-05-04

申请人： SemiWise Limited

发明人： Asen Asenov

IPC分类号： H01L29/10 ,  H01L29/66 ,  H01L29/417 ,  H01L29/78

摘要： A device structure with multiple layers of low temperature epitaxy is disclosed that eliminates source and drain and extension implants, providing a planar interface with abrupt junctions between epitaxial extensions and substrate, mitigating electrostatic coupling between transistor drain and transistor channel and reducing short channel effects. The reduction of channel doping results in improved device performance from reduced impurity scattering and reduction of random dopant induced threshold voltage variations (sigma-Vt). Avoiding implants further reduces device sigma-Vt due to random dopants' diffusion from source and drain extensions, which creates device channel length variations during thermal activation anneal of implanted dopants. The defined transistor structure employs at least two levels of low-temperature epitaxy, and creates a planar interface with various types of transistor substrates resulting in performance improvement. Mixed epitaxial layer growth materials inducing tensile or compressive gate stresses can be advantageously used with the invention to further improve device characteristics.

公开(公告)号：US09373684B2

公开(公告)日：2016-06-21

申请号：US13424745

申请日：2012-03-20

申请人： Asen Asenov ,  Gareth Roy

发明人： Asen Asenov ,  Gareth Roy

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/51 ,  H01L29/78 ,  H01L29/66

CPC分类号： H01L29/105 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66651 ,  H01L29/7833

摘要： Variation resistant metal-oxide-semiconductor field effect transistors (MOSFET) are manufactured using a high-K, metal-gate ‘channel-last’ process. Between spacers formed over a well area having separate drain and source areas, a cavity is formed. Thereafter an ion implant step through the cavity results in a localized increase in well-doping directly beneath the cavity. The implant is activated by a microsecond annealing which causes minimum dopant diffusion. Within the cavity a recess into the well area is formed in which an active region is formed using an un-doped or lightly doped epitaxial layer. A high-K dielectric stack is formed over the lightly doped epitaxial layer, over which a metal gate is formed within the cavity boundaries. In one embodiment of the invention a cap of poly-silicon or amorphous silicon is added on top of the metal gate.

摘要翻译： 使用高K金属栅极“通道最后”工艺制造耐变压金属氧化物半导体场效应晶体管（MOSFET）。 在形成有具有分离的漏极和源极区域的阱区域之间的间隔物之间​​，形成空腔。 此后，通过空腔的离子注入步骤导致在腔的正下方的阱掺杂的局部增加。 通过微秒退火激活植入物，这导致最小的掺杂剂扩散。 在空腔内形成了进入阱区的凹槽，其中使用未掺杂或轻掺杂的外延层形成有源区。 在轻掺杂的外延层上形成高K电介质堆叠，在腔边界内形成金属栅极。 在本发明的一个实施例中，在金属栅极的顶部添加多晶硅或非晶硅的盖。

公开(公告)号：US09312362B2

公开(公告)日：2016-04-12

申请号：US14664595

申请日：2015-03-20

申请人： Gold Standard Simulations Ltd.

发明人： Asen Asenov ,  Gareth Roy

IPC分类号： H01L21/336 ,  H01L29/66 ,  H01L29/51 ,  H01L29/78 ,  H01L29/10 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/8234 ,  H01L29/36

CPC分类号： H01L29/66651 ,  H01L21/02164 ,  H01L21/0262 ,  H01L21/02631 ,  H01L21/02636 ,  H01L21/30604 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/823437 ,  H01L29/105 ,  H01L29/365 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： Variation resistant metal-oxide-semiconductor field effect transistors (MOSFETs) are manufactured using a high-K, metal-gate ‘channel-last’ process. A cavity is formed between spacers formed over a well area having separate drain and source areas, and then a recess into the well area is formed. The active region is formed in the recess, comprising an optional narrow highly doped layer, essentially a buried epitaxial layer, over which a second un-doped or lightly doped layer is formed which is a channel epitaxial layer. The high doping beneath the low doped epitaxial layer can be achieved utilizing low-temperature epitaxial growth with single or multiple delta doping, or slab doping. A high-K dielectric stack is formed over the channel epitaxial layer, over which a metal gate is formed within the cavity boundaries. In one embodiment of the invention a cap of poly-silicon or amorphous silicon is added on top of the metal gate.

摘要翻译： 使用高K，金属栅极“通道最后”工艺制造耐变压金属氧化物半导体场效应晶体管（MOSFET）。 在形成有具有分离的漏极和源极区域的阱区域之间的间隔物之间​​形成空腔，然后形成到阱区域的凹部。 有源区形成在凹部中，包括可选的窄的高掺杂层，基本上是埋入的外延层，在其上形成作为沟道外延层的第二未掺杂或轻掺杂层。 低掺杂外延层下的高掺杂可以利用具有单一或多个δ掺杂或板掺杂的低温外延生长来实现。 在沟道外延层上方形成高K电介质叠层，在腔外界面上形成金属栅极。 在本发明的一个实施例中，在金属栅极的顶部添加多晶硅或非晶硅的盖。

公开(公告)号：US09847404B2

公开(公告)日：2017-12-19

申请号：US14024415

申请日：2013-09-11

申请人： Gold Standard Simulations Ltd. ,  Semi Solutions LLC

发明人： Robert J. Strain ,  Asen Asenov

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L21/308

CPC分类号： H01L29/66795 ,  H01L21/3083 ,  H01L29/1041 ,  H01L29/1054 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7853

摘要： This improved, fluctuation resistant FinFET, with a doped core and lightly doped epitaxial channel region between that core and the gate structure, is confined to the active-gate span because it is based on a channel structure having a limited extent. The improved structure is capable of reducing FinFET random doping fluctuations when doping is used to control threshold voltage, and the channel structure reduces fluctuations attributable to doping-related variations in effective channel length. Further, the transistor design affords better source and drain conductance when compared to prior art FinFETs. Two representative embodiments of the key structure are described in detail.

公开(公告)号：US09263568B2

公开(公告)日：2016-02-16

申请号：US13950810

申请日：2013-07-25

申请人： Gold Standard Simulations Ltd.

发明人： Asen Asenov

IPC分类号： H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L29/10

CPC分类号： H01L29/4983 ,  H01L29/1041 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66651 ,  H01L29/7833

摘要： The structure, and fabrication method thereof, implements a fully depleted silicon-on-insulator (SOI) transistor using a “Channel Last” procedure in which the active channel is a low-temperature epitaxial layer in an etched recess in the SOI silicon film. An optional δ-layer of extremely high doping allows its threshold voltage to be set to a desired value. Based on high-K metal gate last technology, this transistor has reduced threshold uncertainty and superior source and drain conductance. The use of epitaxial layer improves the thickness control of the active channel and reduces the process induced variations. The utilization of active silicon layer that is two or more times thicker than those used in conventional fully depleted SOI devices, reduces the access resistance and improves the on-current of the SOI transistor.

摘要翻译： 其结构及其制造方法使用“通道最后”程序实现完全耗尽的绝缘体上硅（SOI）晶体管，其中有源沟道是SOI硅膜中的蚀刻凹槽中的低温外延层。 极高掺杂的可选的δ层允许其阈值电压被设置为期望值。 基于高K金属栅极技术，该晶体管具有降低的阈值不确定性和优异的源极和漏极电导。 外延层的使用改善了有源沟道的厚度控制，并减少了工艺引起的变化。 活性硅层的使用比常规完全耗尽的SOI器件中使用的厚度大2倍或2倍以上，降低了存取电阻并改善了SOI晶体管的导通电流。

公开(公告)号：US11757002B2

公开(公告)日：2023-09-12

申请号：US17307749

申请日：2021-05-04

申请人： SemiWise Limited

发明人： Asen Asenov

IPC分类号： H01L29/10 ,  H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L29/165

CPC分类号： H01L29/105 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/6656 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/165 ,  H01L29/665 ,  H01L29/7848

摘要： A device structure with multiple layers of low temperature epitaxy is disclosed that eliminates source and drain and extension implants, providing a planar interface with abrupt junctions between epitaxial extensions and substrate, mitigating electrostatic coupling between transistor drain and transistor channel and reducing short channel effects. The reduction of channel doping results in improved device performance from reduced impurity scattering and reduction of random dopant induced threshold voltage variations (sigma-Vt). Avoiding implants further reduces device sigma-Vt due to random dopants' diffusion from source and drain extensions, which creates device channel length variations during thermal activation anneal of implanted dopants. The defined transistor structure employs at least two levels of low-temperature epitaxy, and creates a planar interface with various types of transistor substrates resulting in performance improvement. Mixed epitaxial layer growth materials inducing tensile or compressive gate stresses can be advantageously used with the invention to further improve device characteristics.

公开(公告)号：US11049939B2

公开(公告)日：2021-06-29

申请号：US15226118

申请日：2016-08-02

申请人： SemiWise Limited

发明人： Asen Asenov

IPC分类号： H01L29/10 ,  H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L29/165

摘要： A device structure with multiple layers of low temperature epitaxy is disclosed that eliminates source and drain and extension implants, providing a planar interface with abrupt junctions between epitaxial extensions and substrate, mitigating electrostatic coupling between transistor drain and transistor channel and reducing short channel effects. The reduction of channel doping results in improved device performance from reduced impurity scattering and reduction of random dopant induced threshold voltage variations (sigma-Vt). Avoiding implants further reduces device sigma-Vt due to random dopants' diffusion from source and drain extensions, which creates device channel length variations during thermal activation anneal of implanted dopants. The defined transistor structure employs at least two levels of low-temperature epitaxy, and creates a planar interface with various types of transistor substrates resulting in performance improvement. Mixed epitaxial layer growth materials inducing tensile or compressive gate stresses can be advantageously used with the invention to further improve device characteristics.

公开(公告)号：US09269804B2

公开(公告)日：2016-02-23

申请号：US13950868

申请日：2013-07-25

申请人： Gold Standard Simulations Ltd.

发明人： Asen Asenov

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/78 ,  H01L29/66666 ,  H01L29/7848 ,  H01L29/78684

摘要： The structure and the fabrication methods herein implement a fully depleted, recessed gate silicon-on-insulator (SOI) transistor with reduced access resistance, reduced on-current variability, and strain-increased performance. This transistor is based on an SOI substrate that has an epitaxially grown sandwich of SiGe and Si layers that are incorporated in the sources and drains of the transistors. Assuming a metal gate last complementary metal-oxide semiconductor (CMOS) technology and using the sidewall spacers as a hard mask, a recess under the sacrificial gate reaching all the way through the SiGe layer is created, and the high-K gate stack and metal gate are formed within that recess. The remaining Si region, having a precisely controlled thickness, is the fully depleted channel.

摘要翻译： 本文的结构和制造方法实现了具有降低的存取电阻，降低的导通电流变化性和应变增加性能的完全耗尽的凹陷栅绝缘体上硅（SOI）晶体管。 该晶体管基于具有外延生长的SiGe和Si层的夹层的SOI衬底，其被并入晶体管的源极和漏极中。 假设金属栅最后互补金属氧化物半导体（CMOS）技术并且使用侧壁间隔物作为硬掩模，则在牺牲栅极下方的凹陷到达所有途径通过SiGe层，并且高K栅极堆叠和金属 门形成在该凹槽内。 具有精确控制厚度的剩余Si区域是完全耗尽的通道。