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90 条记录 (耗时 0.027 秒)

    Efficient convergence in iterative decoding
    2.
    发明授权
    Efficient convergence in iterative decoding 有权

    公开(公告)号：US10128869B2

    公开(公告)日：2018-11-13

    申请号：US15156356

    申请日：2016-05-17

    申请人： Apple Inc.

    发明人： Yonathan Tate ,  Moti Teitel

    IPC分类号： H03M13/00 ,  H03M13/11

    摘要： A decoder includes one or more Variable-Node Processors (VNPs) that hold respective variables, and logic circuitry. The logic circuitry is configured to decode a code word of an Error Correction Code (ECC), which is representable by a set of check equations, by performing a sequence of iterations such that each iteration involves processing of at least some of the variables, to hold one or more auxiliary equations derived from the check equations, so that a number of the auxiliary equations is smaller than a number of the check equations, to evaluate the auxiliary equations, during the sequence of iterations, using the variables, and, in response to detecting that the variables satisfy the auxiliary equations, to terminate the sequence of iterations and output the variables as the decoded code word.

    Physical-layer signaling of flow control updates
    3.
    发明授权
    Physical-layer signaling of flow control updates 有权

    公开(公告)号：US09876727B2

    公开(公告)日：2018-01-23

    申请号：US14664944

    申请日：2015-03-23

    申请人： Mellanox Technologies TLV Ltd.

    发明人： Chen Gaist ,  Ran Ravid ,  Liron Mulla ,  Avner Hadash

    IPC分类号： H04L12/801 ,  H04L12/835 ,  H04L12/841 ,  H04L1/00

    CPC分类号： H04L47/35 ,  H04L1/00 ,  H04L1/0002 ,  H04L1/0034 ,  H04L1/18 ,  H04L47/28 ,  H04L47/34

    摘要： A method for communication includes transmitting a sequence of outgoing data blocks from a network node over a communication link to a peer node, and receiving incoming data blocks from the peer node. A control field is added in a predefined location in each of the outgoing data blocks in the sequence by the network node. In at least a first subset of the outgoing data blocks in the sequence, the control field contains error control information, which is capable of causing the peer node to retransmit one or more of the incoming data blocks to the network node, while in at least a second subset of the outgoing data blocks in the sequence, disjoint from the first subset, the control field contains a flow control instruction, configured to cause the peer node to alter a rate of transmission of the incoming data blocks over the link.

    Automatic pre-processing of moderation tasks for moderator-assisted generation of video clips
    6.
    发明授权
    Automatic pre-processing of moderation tasks for moderator-assisted generation of video clips 有权
    自动预处理视频剪辑的主持人辅助生成的节目任务

    公开(公告)号：US09553904B2

    公开(公告)日：2017-01-24

    申请号：US14214964

    申请日：2014-03-16

    申请人： Wochit, Inc.

    发明人： Guy Zisman ,  Eitan Lavi ,  Amotz Hoshen

    IPC分类号： H04L29/06 ,  G06Q10/00 ,  H04L12/18

    CPC分类号： H04L65/4069 ,  G06Q10/00 ,  H04L12/1822

    摘要： A method includes defining multiple moderation tasks, which originate from respective textual articles that are to be automatically converted into respective video clips following moderation by human moderators. The moderation tasks are pre-processed, so as to predict success measures of the corresponding video clips. Delivery of the moderation tasks to the human moderators is prioritized based on the predicted success measures.

    摘要翻译： 一种方法包括定义多个审核任务，这些任务源于相应的文本文章，这些文章将被人类主持人审核后自动转换成相应的视频剪辑。 预处理任务，以预测相应视频剪辑的成功度量。 基于预测的成功措施，优先将适度任务交付给人员主持人。

    Cryptographic operation by applying sub-keys to multiplication units in accordance with galois-field arithmetic
    7.
    发明授权
    Cryptographic operation by applying sub-keys to multiplication units in accordance with galois-field arithmetic 有权
    根据伽罗瓦域算术将子密钥应用于乘法单元进行加密操作

    公开(公告)号：US09525546B2

    公开(公告)日：2016-12-20

    申请号：US14493382

    申请日：2014-09-23

    申请人： Nuvoton Technology Corporation

    发明人： Moshe Alon

    IPC分类号： H04L9/08 ,  H04L9/06 ,  G09C1/00

    CPC分类号： H04L9/0618 ,  G09C1/00 ,  H04L9/065 ,  H04L2209/72

    摘要： A cryptography apparatus includes multiple multiplication units and logic circuitry. The multiplication units are arranged in two or more multiplication levels, and are configured to operate in accordance with Galois-Field (GF) arithmetic over respective Galois fields. The logic circuitry is configured to receive input data whose word-size exceeds a maximal input word-size among the multiplication units, to hold a cryptographic key including multiple sub-keys whose number does not exceed a number of the multiplication units, and to perform a cryptographic operation on the input data by applying the sub-keys to the multiplication units.

    摘要翻译： 密码学装置包括多个乘法单元和逻辑电路。 乘法单元被布置成两个或多个乘法电平，并且被配置为根据各个伽罗瓦域的伽罗瓦域（GF）运算进行运算。 逻辑电路被配置为接收字长超过乘法单元中的最大输入字大小的输入数据，以保存包括多个子密钥的加密密钥，该子密钥的编号不超过乘法单元的数目，并执行 通过将子键应用于乘法单元来对输入数据进行加密操作。

    Packet steering
    8.
    发明授权
    Packet steering 有权
    包转向

    公开(公告)号：US09397960B2

    公开(公告)日：2016-07-19

    申请号：US13291143

    申请日：2011-11-08

    申请人： Nir Haim Arad ,  Noam Bloch ,  Ariel Shahar ,  Hillel Chapman ,  Amir Wated

    发明人： Nir Haim Arad ,  Noam Bloch ,  Ariel Shahar ,  Hillel Chapman ,  Amir Wated

    IPC分类号： H04L12/931 ,  H04L12/54 ,  H04L12/721

    CPC分类号： H04L45/74 ,  H04L45/38 ,  H04L45/745 ,  H04L47/10 ,  H04L49/351 ,  H04L49/355 ,  H04L49/358 ,  H04L49/70

    摘要： A method for steering packets, including receiving a packet and determining parameters to be used in steering the packet to a specific destination, in one or more initial steering stages, based on one or more packet specific attributes. The method further includes determining an identity of the specific destination of the packet in one or more subsequent steering stages, governed by the parameters determined in the one or more initial stages and one or more packet specific attributes, and forwarding the packet to the determined specific destination.

    摘要翻译： 一种用于在一个或多个初始转向阶段中基于一个或多个分组特定属性来指导分组的方法，包括接收分组并确定要用于指导分组到特定目的地的参数。 该方法还包括确定一个或多个后续转向级中的分组的特定目的地的身份，由在一个或多个初始阶段中确定的参数和一个或多个分组特定属性来管理，以及将分组转发到所确定的特定 目的地。

    Identifying word-line-to-substrate and word-line-to-word-line short-circuit events in a memory block
    9.
    发明授权
    Identifying word-line-to-substrate and word-line-to-word-line short-circuit events in a memory block 有权
    识别存储器块中的字线到基板和字线到字线的短路事件

    公开(公告)号：US09330783B1

    公开(公告)日：2016-05-03

    申请号：US14572818

    申请日：2014-12-17

    申请人： APPLE INC.

    发明人： Barak Rotbard ,  Avraham Poza Meir ,  Eyal Gurgi ,  Yael Shur ,  Barak Baum

    IPC分类号： G11C29/00 ,  G11C29/02 ,  G11C16/26 ,  G11C16/14

    CPC分类号： G11C29/025 ,  G11C29/006 ,  G11C2029/1202

    摘要： An apparatus includes a memory and a memory controller. The memory includes a memory block that includes memory cells connected by word lines. The memory controller is configured to store data in the memory cells, and to identify a suspected short-circuit event in the memory block by recognizing a deviation of a performance characteristic of at least a given word line in the memory block relative to the performance characteristic of remaining word lines in the memory block.

    摘要翻译： 一种装置包括存储器和存储器控制器。 该存储器包括一个包含通过字线连接的存储器单元的存储块。 存储器控制器被配置为将数据存储在存储器单元中，并且通过识别存储器块中的至少给定字线的性能特性相对于性能特性的偏差来识别存储器块中的可疑短路事件 剩余字线在存储器块中。

    Sharing address translation between CPU and peripheral devices
    10.
    发明授权
    Sharing address translation between CPU and peripheral devices 有权
    共享CPU和外围设备之间的地址转换

    公开(公告)号：US09298642B2

    公开(公告)日：2016-03-29

    申请号：US13665946

    申请日：2012-11-01

    申请人： MELLANOX TECHNOLOGIES LTD.

    发明人： Michael Kagan ,  Noam Bloch ,  Liran Liss ,  Shachar Raindel

    IPC分类号： G06F12/00 ,  G06F12/10

    CPC分类号： G06F12/1081

    摘要： A method for memory access includes maintaining in a host memory, under control of a host operating system running on a central processing unit (CPU), respective address translation tables for multiple processes executed by the CPU. Upon receiving, in a peripheral device, a work item that is associated with a given process, having a respective address translation table in the host memory, and specifies a virtual memory address, the peripheral device translates the virtual memory address into a physical memory address by accessing the respective address translation table of the given process in the host memory. The work item is executed in the peripheral device by accessing data at the physical memory address in the host memory.

    摘要翻译： 一种用于存储器访问的方法包括在主机操作系统在中央处理单元（CPU）上运行的主机操作系统的控制下维护主机存储器，用于由CPU执行的多个进程的各自的地址转换表。 在外围设备中接收与给定进程相关联的工作项，在主机存储器中具有相应的地址转换表，并指定虚拟存储器地址时，外围设备将虚拟存储器地址转换为物理存储器地址 通过访问主机存储器中给定进程的相应地址转换表。 通过访问主机存储器中的物理存储器地址上的数据，在外围设备中执行工作项。