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    Management of peak power consumed by multiple memory devices
    1.
    发明授权
    Management of peak power consumed by multiple memory devices 有权

    公开(公告)号：US09817595B2

    公开(公告)日：2017-11-14

    申请号：US15008470

    申请日：2016-01-28

    Applicant: APPLE INC.

    Inventor： Barak Rotbard ,  Itay Sagron

    IPC: G06F13/00 ,  G06F3/06

    CPC classification number: G06F3/0625 ,  G06F3/064 ,  G06F3/0673 ,  G11C16/30

    Abstract: A controller includes an interface and a processor. The interface is configured to communicate with one or more memory devices that include multiple memory blocks. The processor is configured to hold information regarding power consumption of the memory blocks, to group at least some of the memory blocks into one or more storage groups, based on the information, such that the memory blocks in each storage group jointly consume less than a predefined power limit when the memory blocks in the storage group are applied a storage operation in parallel, and to apply the storage operation, in parallel, to the memory blocks in a selected storage group.

    ADVANCED PROGRAMMING VERIFICATION SCHEMES FOR MEMORY CELLS
    3.
    发明申请
    ADVANCED PROGRAMMING VERIFICATION SCHEMES FOR MEMORY CELLS 审中-公开
    用于记忆细胞的高级编程验证方案

    公开(公告)号：US20150193293A1

    公开(公告)日：2015-07-09

    申请号：US14662470

    申请日：2015-03-19

    Applicant: Apple Inc.

    Inventor： Eyal Gurgi ,  Yoav Kasorla ,  Barak Rotbard ,  Shai Ojalvo

    IPC: G06F11/07

    CPC classification number: G11C29/38 ,  G06F11/07 ,  G06F11/073 ,  G06F11/0772 ,  G06F11/263 ,  G11C11/1677 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5678 ,  G11C13/0035 ,  G11C13/0064 ,  G11C13/0069 ,  G11C13/0097 ,  G11C16/10 ,  G11C16/3459 ,  G11C29/12015 ,  G11C29/44 ,  G11C29/50012

    Abstract: A method for data storage includes receiving in a memory device data for storage in a group of memory cells. The data is stored in the group by performing a Program and Verify (P&V) process, which applies to the memory cells in the group a sequence of programming pulses and compares respective analog values of the memory cells in the group to respective verification thresholds. Immediately following successful completion of the P&V process, a mismatch between the stored data and the received data is detected in the memory device. An error in storage of the data is reported responsively to the mismatch.

    Abstract translation: 一种用于数据存储的方法包括在存储器装置中接收用于存储在一组存储器单元中的数据。 通过执行程序和验证（P＆V）过程将数据存储在组中，该过程适用于组中的存储器单元的编程脉冲序列，并将组中的存储器单元的各自的模拟值与相应的验证阈值进行比较。 在P＆V进程成功完成之后，在存储器件中检测到存储的数据与接收到的数据之间的不匹配。 响应于不匹配报告数据存储错误。

    Hierarchical data storage system
    10.
    发明授权
    Hierarchical data storage system 有权
    分层数据存储系统

    公开(公告)号：US09405705B2

    公开(公告)日：2016-08-02

    申请号：US14548664

    申请日：2014-11-20

    Applicant: Apple Inc.

    Inventor： Michael Shachar ,  Barak Rotbard ,  Oren Golov ,  Uri Perlmutter ,  Dotan Sokolov ,  Julian Vlaiko ,  Yair Schwartz

    IPC: G06F12/00 ,  G06F12/12 ,  G06F12/06 ,  G06F13/16 ,  G06F12/02 ,  G06F3/06 ,  G06F13/18

    CPC classification number: G06F12/12 ,  G06F3/0628 ,  G06F3/0683 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/0638 ,  G06F13/1657 ,  G06F13/1668 ,  G06F13/18 ,  G06F2212/1024 ,  G06F2212/7208

    Abstract: A data storage system includes a plurality of non-volatile memory devices arranged in one or more sets, a main controller and one or more processors. The main controller is configured to accept commands from a host and to convert the commands into recipes. Each recipe includes a list of multiple memory operations to be performed sequentially in the non-volatile memory devices belonging to one of the sets. Each of the processors is associated with a respective set of the non-volatile memory devices, and is configured to receive one or more of the recipes from the main controller and to execute the memory operations specified in the received recipes in the non-volatile memory devices belonging to the respective set.

    Abstract translation: 数据存储系统包括以一个或多个集合排列的多个非易失性存储器件，主控制器和一个或多个处理器。 主控制器配置为接受来自主机的命令，并将命令转换为配方。 每个配方包括要在属于其中一个组的非易失性存储器件中顺序执行的多个存储器操作的列表。 每个处理器与相应的一组非易失性存储器设备相关联，并且被配置为从主控制器接收一个或多个配方并且执行在非易失性存储器中接收的配方中指定的存储器操作 属于相应集合的设备。

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