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280 条记录 (耗时 0.032 秒)

    Method, system and device for non-volatile memory device operation
    3.
    发明授权
    Method, system and device for non-volatile memory device operation 有权

    公开(公告)号：US10861541B2

    公开(公告)日：2020-12-08

    申请号：US16153680

    申请日：2018-10-05

    申请人： ARM Ltd.

    发明人： Bal S. Sandhu ,  Cezary Pietrzyk ,  George McNeil Lattimore

    IPC分类号： G11C13/00 ,  G11C14/00

    摘要： Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a non-volatile memory device may be placed in any one of multiple memory states in a write operation by controlling a current and a voltage applied to terminals of the non-volatile memory device. For example, a write operation may apply a programming signal across terminals of non-volatile memory device having a particular current and a particular voltage for placing the non-volatile memory device in a particular memory state.

    I/O driven data routing and cache allocation
    4.
    发明授权
    I/O driven data routing and cache allocation 有权

    公开(公告)号：US10733106B2

    公开(公告)日：2020-08-04

    申请号：US15801995

    申请日：2017-11-02

    申请人： ARM LTD

    发明人： Pavel Shamis ,  Alejandro Rico Carro

    IPC分类号： G06F12/0871 ,  G06F12/0811 ,  G06F3/06 ,  G06F12/128 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/0813 ,  G06F12/123 ,  G06F12/084

    摘要： A method and apparatus are provided for automatic routing of messages in a data processing system. An incoming message at an input/output (I/O) interface of the data processing system includes a message identifier and payload data. Match information, including an indicator or whether the message identifier of the incoming message matches an identifier of a request in a receive queue (RQ), is used to determine a destination for the incoming message. The incoming message is forwarded to the determined destination. Information, such as payload size and RQ position, may be used to determine allocation of the payload within a cache or cache hierarchy.

    Cache-based communication between execution threads of a data processing system
    6.
    发明授权
    Cache-based communication between execution threads of a data processing system 有权

    公开(公告)号：US10474575B2

    公开(公告)日：2019-11-12

    申请号：US15483036

    申请日：2017-04-10

    申请人： ARM Ltd

    发明人： Jonathan Curtis Beard ,  Eric Van Hensbergen

    IPC分类号： G06F11/10 ,  G06F12/0831 ,  G06F12/1045 ,  G06F12/0875 ,  G06F13/42 ,  G06F12/0813 ,  G06F13/16

    摘要： A virtual link buffer provides communication between processing threads or cores. A first cache is accessible by a first processing device and a second cache accessible by a second processing device. An interconnect structure couples between the first and second caches and includes a link controller. A producer cache line in the first cache stores data produced by the first processing device and the link controller transfers data in the producer cache line to a consumer cache line in the second cache. Each new data element is stored at a location in the producer cache line indicated by a store position or tail indicator that is stored at a predetermined location in the same cache line. Transferred data are loaded from a location in the consumer cache line indicated by a load position or head indicator that is stored at a predetermined location in the same consumer cache line.

    Memory node controller
    7.
    发明授权
    Memory node controller 有权

    公开(公告)号：US10467159B2

    公开(公告)日：2019-11-05

    申请号：US15650008

    申请日：2017-07-14

    申请人： ARM LTD

    发明人： Jonathan Curtis Beard ,  Roxana Rusitoru ,  Curtis Glenn Dunham

    IPC分类号： G06F13/16 ,  H04L12/931 ,  H04L12/947 ,  G06F12/0817 ,  G06F12/1036 ,  G06F12/1072 ,  G06F12/1081

    摘要： A memory node controller for a node of a data processing network, the network including at least one computing device and at least one data resource, each data resource addressed by a physical address. The node is configured to couple the at least one computing device with the at least one data resource. Elements of the data processing network are addressed via a system address space. The memory node controller includes a first interface to the at least one data resource, a second interface to the at least one computing device, and a system to physical address translator cache configured to translate a system address in the system address space to a physical address in the physical address space of the at least one data resource.

    Method and apparatus for hardware management of multiple memory pools
    8.
    发明授权
    Method and apparatus for hardware management of multiple memory pools 有权

    公开(公告)号：US10417141B2

    公开(公告)日：2019-09-17

    申请号：US15601541

    申请日：2017-05-22

    申请人： ARM Ltd

    发明人： Andrea Pellegrini ,  Kshitij Sudan ,  Ali Saidi ,  Wendy Arnott Elsasser

    IPC分类号： G06F12/00 ,  G06F12/128 ,  G06F12/0808 ,  G06F12/1027 ,  G06F12/1009 ,  G06F12/12

    摘要： A data processing system for managing at least first and second memories includes a caching manager and a translation lookaside buffer (TLB). The caching manager comprises hardware configured to transfer data between the memories and is configured to monitor accesses to the first memory by a processing device and transfer data in a frequently accessed region at a first address in the first memory to a region at a second address in the second memory. When the data has not been transferred to the second memory, the TLB stores a virtual address and a corresponding address in the first memory. However, when the data has been transferred to the second memory, the TLB stores the virtual address and a corresponding address in the second memory. A mapping between the addresses in the first and second memories may be stored in a shadow-address table.