公开(公告)号：US20050110551A1

公开(公告)日：2005-05-26

申请号：US10707171

申请日：2003-11-25

申请人： Anthony Bonaccio ,  Allen Haar ,  Michael Sorna ,  Ivan Wemple ,  Stephen Wyatt

发明人： Anthony Bonaccio ,  Allen Haar ,  Michael Sorna ,  Ivan Wemple ,  Stephen Wyatt

IPC分类号： G05F1/10 ,  G05F3/02 ,  H03K17/16 ,  H03L5/00

CPC分类号： G11C5/14 ,  H01L23/50 ,  H01L2924/0002 ,  H03K17/164 ,  H01L2924/00

摘要： A structure and method for damping LC (inductance-capacitance) ringing in integrated circuit (IC) power distribution systems. The structure comprises a resistance electrically connected in parallel with a plurality of electrical switches. The resistance and electrical switches are electrically connected in series with the package and on-chip power distribution circuit. When on-chip switching activity creates a sudden and appreciable change in IC power demand the electrical switches are opened to temporarily increase the resistance in series with the power supply. This serves to dampen the power-distribution LC ringing. Later, the electrical switches are closed to shunt the series resistance and reduce the level of steady-state voltage drop in the power structure.

摘要翻译： 用于阻尼集成电路（IC）配电系统中LC（电感 - 电容）振铃的结构和方法。 该结构包括与多个电开关并联电连接的电阻。 电阻和电气开关与封装和片上配电电路串联电连接。 当片上切换活动产生IC功率需求的突然和明显的变化时，电开关被打开以临时增加与电源串联的电阻。 这用于抑制功率分配LC振铃。 之后，电开关闭合以分流串联电阻并降低电源结构中稳态电压降的水平。

公开(公告)号：US20070115019A1

公开(公告)日：2007-05-24

申请号：US11164040

申请日：2005-11-08

申请人： Anthony Bonaccio ,  Allen Haar ,  Joseph Iadanza ,  Douglas Stout ,  Ivan Wemple

发明人： Anthony Bonaccio ,  Allen Haar ,  Joseph Iadanza ,  Douglas Stout ,  Ivan Wemple

IPC分类号： G01R31/26

CPC分类号： G01R31/2884 ,  G01R35/005

摘要： A method for altering circuit characteristics to make them independent of processing parameters of devices within an integrated circuit is disclosed. A process parameter is measured by a kerf or on-chip built-in test on a selective set of chip on a wafer, and the results are stored on a storage device within each respective chip. Then, for each of the remaining chips, a two-dimensional interpolation is performed to determine the process parameter value for the respective chip based on the measured value. The interpolated values are recorded along with the coordinates of the chip in an efuse control file. Such information is subsequently stored into an efuse module within the chip. On-chip digital control structures are used to adjust certain operational characteristics of a functional component within the chip based on the information stored in the efuse module.

摘要翻译： 公开了一种用于改变电路特性以使它们与集成电路内的器件的处理参数无关的方法。 通过在晶片上的选择性芯片组上的切口或片上内置测试来测量工艺参数，并将结果存储在每个相应芯片内的存储装置上。 然后，对于剩余的每个芯片，执行二维内插，以基于测量值确定各个芯片的处理参数值。 内插值与芯片在efuse控制文件中的坐标一起被记录。 这样的信息随后被存储在芯片内的efuse模块中。 片上数字控制结构用于根据存储在efuse模块中的信息来调整芯片内的功能组件的某些操作特性。

公开(公告)号：US20070220468A1

公开(公告)日：2007-09-20

申请号：US11752035

申请日：2007-05-22

申请人： Allen Haar ,  Joseph Iadanza ,  Sebastian Ventrone ,  Ivan Wemple

发明人： Allen Haar ,  Joseph Iadanza ,  Sebastian Ventrone ,  Ivan Wemple

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： A method for converting globally clock-gated circuits to locally clock-gated circuits is disclosed. A timing analysis is initially performed on an integrated circuit (IC) design to generate a slack time report for all globally clock-gated circuits within the IC design. Based on their respective slack time indicated in the slack time report, all globally clock-gated circuits that should be connected to locally generated clocks are identified. After disconnecting from a global clock tree, each of the identified globally clock-gated circuits is subsequently connected to a locally generated clock having a clock delay comparable to its slack time indicated in the slack time report.

摘要翻译： 公开了一种将全局时钟选通电路转换为本地时钟门控电路的方法。 最初在集成电路（IC）设计上执行时序分析，以便为IC设计中的所有全局时钟门控电路生成松弛时间报告。 根据松弛时间报告中指定的各自的松弛时间，可以识别应连接到本地生成的时钟的所有全局时钟选通电路。 在与全局时钟树断开连接之后，所识别的全局时钟门控电路中的每一个随后连接到具有与其在松弛时间报告中指示的松弛时间相当的时钟延迟的本地产生的时钟。

公开(公告)号：US20060101362A1

公开(公告)日：2006-05-11

申请号：US10904397

申请日：2004-11-08

申请人： Allen Haar ,  Joseph Iadanza ,  Sebastian Ventrone ,  Ivan Wemple

发明人： Allen Haar ,  Joseph Iadanza ,  Sebastian Ventrone ,  Ivan Wemple

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5045

摘要： A method for converting globally clock-gated circuits to locally clock-gated circuits is disclosed. A timing analysis is initially performed on an integrated circuit (IC) design to generate a slack time report for all globally clock-gated circuits within the IC design. Based on their respective slack time indicated in the slack time report, all globally clock-gated circuits that should be connected to locally generated clocks are identified. After disconnecting from a global clock tree, each of the identified globally clock-gated circuits is subsequently connected to a locally generated clock having a clock delay comparable to its slack time indicated in the slack time report.

摘要翻译： 公开了一种将全局时钟选通电路转换为本地时钟门控电路的方法。 最初在集成电路（IC）设计上执行时序分析，以便为IC设计中的所有全局时钟门控电路生成松弛时间报告。 根据松弛时间报告中指定的各自的松弛时间，可以识别应连接到本地生成的时钟的所有全局时钟选通电路。 在与全局时钟树断开连接之后，所识别的全局时钟门控电路中的每一个随后连接到具有与其在松弛时间报告中指示的松弛时间相当的时钟延迟的本地产生的时钟。

公开(公告)号：US20050093620A1

公开(公告)日：2005-05-05

申请号：US10605855

申请日：2003-10-31

申请人： Shiu Ho ,  Ivan Wemple ,  Stephen Wyatt

发明人： Shiu Ho ,  Ivan Wemple ,  Stephen Wyatt

IPC分类号： H01L27/02 ,  H03K17/691 ,  H03K19/0175 ,  H03B1/00

CPC分类号： H03K19/017545 ,  H01L27/0251 ,  H03K17/691

摘要： An integrated circuit designed to reduce on-chip noise coupling. In one embodiment, circuit (60) includes the following: a circuit transformer (62) capable of converting a noise sensitive input reference clock signal to an output signal having a voltage compatible with a predetermined sink voltage logic level; and a biased receiver network (64) having a PFET current mirror (74) coupled with a NFET current (72), the biased receiver transistor network designed to multiply the transformer signal to offset a mutual coupling loss of the transformer. In at least one alternative embodiment, the input reference clock signal originates at an off-chip clock generator circuit (42) and the output signal from receiver (64) is input to a PLL (44). In another alternative embodiment, the transformer is a monolithic integrated transformer. Another alternative embodiment of the present invention is a method of reducing on-chip noise coupling.

摘要翻译： 一种集成电路，旨在减少片内噪声耦合。 在一个实施例中，电路（60）包括以下：电路变压器（62），其能够将噪声敏感的输入参考时钟信号转换成具有与预定接收电压逻辑电平兼容的电压的输出信号; 以及偏置的接收器网络（64），其具有与NFET电流（72）耦合的PFET电流镜（74），所述偏置的接收器晶体管网络被设计为将变压器信号乘以偏移变压器的互耦合损耗。 在至少一个备选实施例中，输入参考时钟信号起始于片外时钟发生器电路（42），并且来自接收机（64）的输出信号被输入到PLL（44）。 在另一替代实施例中，变压器是单片集成变压器。 本发明的另一替代实施例是减少片上噪声耦合的方法。

公开(公告)号：US20050108667A1

公开(公告)日：2005-05-19

申请号：US10707068

申请日：2003-11-19

申请人： Joseph Iadanza ,  Raminderpal Singh ,  Sebastian Ventrone ,  Ivan Wemple

发明人： Joseph Iadanza ,  Raminderpal Singh ,  Sebastian Ventrone ,  Ivan Wemple

IPC分类号： G06F17/50 ,  G06G7/62

CPC分类号： G06F17/5045

摘要： A method for designing an integrated circuit having multiple voltage domains, including: (a) generating a logical integrated circuit design from information contained in a high-level design file, the high-level design file defining global connection declarations and voltage domain connection declarations; (b) synthesizing the logical integrated circuit design into a synthesized integrated circuit design based upon the logical integrated circuit design, information in a preferred components file and information in a voltage domain definition file; (c) generating a noise model from the synthesized integrated circuit design based on information in the voltage domain definition file and a design constraint file; and (d) simulating the noise model against constraints in the design constraint file and constraints in a circuit level profile file to determine if the synthesized integrated circuit design meets predetermined noise simulation targets.

摘要翻译： 一种用于设计具有多个电压域的集成电路的方法，包括：（a）从包含在高级设计文件中的信息，定义全局连接声明和电压域连接声明的高级设计文件生成逻辑集成电路设计; （b）基于逻辑集成电路设计，优选组件文件中的信息和电压域定义文件中的信息，将逻辑集成电路设计合成为合成集成电路设计; （c）基于电压域定义文件和设计约束文件中的信息从合成的集成电路设计中产生噪声模型; 和（d）根据设计约束文件中的约束和电路级配置文件中的约束模拟噪声模型，以确定合成的集成电路设计是否满足预定的噪声模拟目标。

公开(公告)号：US20070204244A1

公开(公告)日：2007-08-30

申请号：US11307894

申请日：2006-02-27

申请人： Timothy Lehner ,  Richard Kimmel ,  Ali Sadigh ,  Emrah Acar ,  Ying Liu ,  Ivan Wemple

发明人： Timothy Lehner ,  Richard Kimmel ,  Ali Sadigh ,  Emrah Acar ,  Ying Liu ,  Ivan Wemple

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： A method and a system for validating initial conditions (ICs) generally provided by a user when simulating a VLSI circuit are described. Inconsistent ICs sets are detected and replaced by consistent subsets thereof. The method selects the resistance and source values in a Norton or Thevenin circuit used to enforce the IC, and detects when specified ICs are inconsistent while preserving critical or fragile ICs when a two DC-pass approach is used. It further correlates the set of consistent ICs thus obtained with an equivalent circuit and simultaneously provides an input for future use. This allows a user to be notified and given a measure of how bad the inconsistencies are. Detecting inconsistencies is achieved either by measuring the holding current or by measuring the voltage drift if the two DC-pass approach is used.

摘要翻译： 描述用于在模拟VLSI电路时通常由用户提供的用于验证初始条件（IC）的方法和系统。 检测不一致的IC集合，并由其一致的子集替换。 该方法选择用于强制IC的Norton或Thevenin电路中的电阻和源值，并在使用两个DC-pass方法时检测指定的IC是否不一致，同时保留关键或易碎的IC。 它进一步将由此获得的一组一致的IC与等效电路相关联，并同时提供用于将来使用的输入。 这允许用户被通知，并给出了不一致的程度。 通过测量保持电流或通过使用两个直流通路的方法测量电压漂移来实现检测不一致。

公开(公告)号：US20070226667A1

公开(公告)日：2007-09-27

申请号：US11277385

申请日：2006-03-24

申请人： Thomas Chadwick ,  Margaret Charlebois ,  David Hathaway ,  Jason Rotella ,  Douglas Stout ,  Ivan Wemple

发明人： Thomas Chadwick ,  Margaret Charlebois ,  David Hathaway ,  Jason Rotella ,  Douglas Stout ,  Ivan Wemple

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5031

摘要： A method, system and computer program product for analyzing and modifying a static timing slack of a timing path in a static timing analysis of a design of an integrated circuit (IC) with a transient power supply are disclosed. A static timing slack analysis is performed at a selected endpoint in an IC to obtain a candidate timing path leading to the endpoint with a worst static timing slack. A transient static timing slack is determined for the candidate timing path for each clock cycle of a clock signal under the transient power supply. The determined transient static timing slack is used to adjust the timing of the IC and to modify the static timing slack of the candidate timing path.

摘要翻译： 公开了一种用于在具有瞬态电源的集成电路（IC）的设计的静态时序分析中分析和修改定时路径的静态定时松弛的方法，系统和计算机程序产品。 在IC中的选定端点处执行静态时序松弛分析，以获得以最差的静态时序松弛通向端点的候选定时路径。 瞬态电源下的时钟信号的每个时钟周期的候选定时路径确定瞬态静态时序松弛。 使用确定的瞬态静态时序松弛来调整IC的定时并修改候选定时路径的静态时序松弛。

公开(公告)号：US06832361B2

公开(公告)日：2004-12-14

申请号：US09862427

申请日：2001-05-21

申请人： John Maxwell Cohn ,  Scott Whitney Gould ,  Ronald Dennis Rose ,  Ivan Wemple ,  Paul Steven Zuchowski

发明人： John Maxwell Cohn ,  Scott Whitney Gould ,  Ronald Dennis Rose ,  Ivan Wemple ,  Paul Steven Zuchowski

IPC分类号： G06F1750

CPC分类号： G06F17/5022

摘要： A method and system for analyzing power distribution in an integrated circuit chip includes dividing a clock cycle of the integrated circuit chip into a plurality of time periods, dividing the integrated circuit chip into a plurality of cells, performing a static timing analysis for the plurality of cells to obtain current waveform data for each cell and each time period, and performing a power distribution analysis using the current waveform data.

摘要翻译： 一种用于分析集成电路芯片中的功率分配的方法和系统，包括将集成电路芯片的时钟周期划分成多个时间段，将集成电路芯片分成多个单元，对多个单元执行静态时序分析 单元，以获得每个单元和每个时间段的电流波形数据，以及使用当前波形数据进行功率分布分析。

公开(公告)号：US20060229828A1

公开(公告)日：2006-10-12

申请号：US11095327

申请日：2005-03-31

申请人： David Hathaway ,  Douglas Stout ,  Ivan Wemple

发明人： David Hathaway ,  Douglas Stout ,  Ivan Wemple

IPC分类号： G06F19/00

CPC分类号： G06F17/5036

摘要： A method of, and a system for, determining an extreme value of a voltage dependent parameter of an integrated circuit design is provided. The method includes determining a plurality of current waveforms, each of the plurality of waveforms corresponding to one of a plurality of aggressor objects in the design of the integrated circuit; applying each of the plurality of current waveforms to a subset of the plurality of power bus nodes, the subset of the plurality of power bus nodes being designed to supply power to a corresponding one of the plurality of aggressor objects; determining a plurality of voltage waveforms, each of the plurality of voltage waveforms being at one of the plurality of power bus nodes and corresponding to one of the plurality of current waveforms; using the plurality of voltage waveforms to determine the extreme value.

摘要翻译： 提供了一种用于确定集成电路设计的电压相关参数的极值的方法和系统。 所述方法包括确定多个电流波形，所述多个波形中的每一个对应于所述集成电路的设计中的多个侵略对象中的一个; 将所述多个电流波形中的每一个应用于所述多个电力总线节点的子集，所述多个电力总线节点的子集被设计为向所述多个侵权者对象中的相应一个提供电力; 确定多个电压波形，所述多个电压波形中的每一个在所述多个电力总线节点中的一个处并且对应于所述多个电流波形中的一个; 使用多个电压波形来确定极值。