公开(公告)号：US20050058005A1

公开(公告)日：2005-03-17

申请号：US10747217

申请日：2003-12-30

申请人： Assaf Shappir ,  Dror Avni ,  Boaz Eitan

发明人： Assaf Shappir ,  Dror Avni ,  Boaz Eitan

IPC分类号： G11C16/02 ,  G11C16/04 ,  G11C16/34 ,  G11C29/02 ,  G11C29/50 ,  G11C8/02

CPC分类号： G11C29/50 ,  G11C16/04 ,  G11C16/3436 ,  G11C16/3445 ,  G11C16/3459 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C29/50004

摘要： A method and a system for operating bits of memory cells in a memory array, the method including applying a first operating pulse to a terminal of a first cell, the first operating pulse is intended to place the first cell into a predefined state; and applying a second operating pulse to a terminal of a second cell in the set, the second operating pulse is intended to place the second cell to the predefined state, and the pulse characteristics of the second operating pulse are a function of the response of the first cell to the first operating pulse.

摘要翻译： 一种用于操作存储器阵列中的存储器单元的位的方法和系统，所述方法包括将第一操作脉冲施加到第一单元的端子，所述第一操作脉冲旨在将所述第一单元放置在预定状态; 以及将第二操作脉冲施加到所述组中的第二小区的终端，所述第二操作脉冲旨在将所述第二小区置于所述预定状态，并且所述第二操作脉冲的脉冲特性是所述第二操作脉冲的响应的函数 第一个电池到第一个工作脉冲。

公开(公告)号：US5493683A

公开(公告)日：1996-02-20

申请号：US997879

申请日：1992-12-29

申请人： Philip L. Cloud ,  Dror Avni

发明人： Philip L. Cloud ,  Dror Avni

IPC分类号： G06F1/32 ,  G06F9/30 ,  G06F9/38 ,  G06F1/18

CPC分类号： G06F9/3881 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/3296 ,  G06F9/30101 ,  Y02B60/1221 ,  Y02B60/1285

摘要： A power conversation apparatus in a computer system. This apparatus includes an identification register in a processor comprising a contents including a plurality of flags for identifying the characteristics of the processor. One of these characteristics may be whether the processor includes static logic devices. In such systems, the clock connected to the processor may be halted, without the corruption of data in the processor. Other characteristics may include whether the processor is clocked at the same rate as the system, or whether the processor may operate on a lower voltage power source. The apparatus further comprises a transmission circuit for transferring the contents of the identification register from the processor to a system coupled to the processor upon the receipt of a first code. The apparatus also comprises a reception circuit in the system for receiving the contents of the identification register, a storage circuit for storing the contents of the identification register, a determination circuit in the system for determining the contents of the storage circuit, such a logic unit, and a clock halt circuit for stopping the clock. In this manner, various characteristics of the processor may be determined allowing the system to be reconfigured and power conserved appropriately.

摘要翻译： 计算机系统中的电力谈话装置。 该装置包括处理器中的识别寄存器，其包括用于识别处理器的特性的多个标志的内容。 这些特征之一可以是处理器是否包括静态逻辑器件。 在这样的系统中，连接到处理器的时钟可以停止，而不会在处理器中损坏数据。 其他特征可以包括处理器是以与系统相同的速率计时，还是处理器是否可以在较低电压电源上操作。 该装置还包括传输电路，用于在接收到第一代码时将识别寄存器的内容从处理器传送到耦合到处理器的系统。 该装置还包括用于接收识别寄存器的内容的系统中的接收电路，用于存储识别寄存器的内容的存储电路，用于确定存储电路的内容的系统中的确定电路，诸如逻辑单元 以及用于停止时钟的时钟停止电路。 以这种方式，可以确定处理器的各种特性，允许系统被适当地重新配置和功率保存。

公开(公告)号：US06937521B2

公开(公告)日：2005-08-30

申请号：US10155216

申请日：2002-05-28

申请人： Dror Avni ,  Boaz Eitan

发明人： Dror Avni ,  Boaz Eitan

IPC分类号： G11C16/02 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  G11C16/28 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C16/06

CPC分类号： G11C11/5671 ,  G11C16/0475 ,  G11C16/10 ,  G11C16/14 ,  G11C16/28 ,  G11C16/3468 ,  G11C16/3481

摘要： A method for programming and erasing a memory array includes the step of adapting programming or erase pulses to the current state of the memory array. In one embodiment, the step of adapting includes the steps of determining the voltage level of the programming pulse used to program a fast bit of the memory array and setting an initial programming level of the memory array to a level in the general vicinity of the programming level of the fast bit. For erasure, the method includes the steps of determining erase conditions of the erase pulse used to erase a slowly erasing bit of said memory array and setting initial erase conditions of said memory array to the general vicinity of said erase conditions of said slowly erasing bit. In another embodiment of the array, the step of adapting includes the steps of measuring the current threshold level of a bit to within a given range and selecting an incremental voltage level of a next programming or erase pulse for the bit in accordance with the measured current threshold level.

摘要翻译： 用于编程和擦除存储器阵列的方法包括将编程或擦除脉冲适配到存储器阵列的当前状态的步骤。 在一个实施例中，适配步骤包括以下步骤：确定用于对存储器阵列的快速位进行编程的编程脉冲的电压电平，并将存储器阵列的初始编程电平设置为编程的大致附近的电平 水平的快速位。 为了擦除，该方法包括以下步骤：确定用于擦除所述存储器阵列的缓慢擦除位的擦除脉冲的擦除条件，并将所述存储器阵列的初始擦除条件设置为所述缓慢擦除位的所述擦除条件的附近。 在阵列的另一实施例中，适配步骤包括以下步骤：将位的电流阈值电平测量到给定范围内，并根据测量的电流选择位的下一个编程或擦除脉冲的增量电压电平 门限等级。

公开(公告)号：US5655125A

公开(公告)日：1997-08-05

申请号：US551320

申请日：1995-11-01

申请人： Philip L. Cloud ,  Dror Avni

发明人： Philip L. Cloud ,  Dror Avni

IPC分类号： G06F1/32 ,  G06F9/30 ,  G06F9/38 ,  G06F1/18

CPC分类号： G06F9/3881 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/3296 ,  G06F9/30101 ,  Y02B60/1221 ,  Y02B60/1285

摘要： A power conservation apparatus in a computer system. This apparatus includes an identification register in a processor comprising a contents including a plurality of flags for identifying the characteristics of the processor. One of these characteristics may be whether the processor includes static logic devices. In such systems, the clock connected to the processor may be halted, without the corruption of data in the processor. Other characteristics may include whether the processor is clocked at the same rate as the system, or whether the processor may operate on a lower voltage power source. The apparatus further comprises a transmission circuit for transferring the contents of the identification register from the processor to a system coupled to the processor upon the receipt of a first code. The apparatus also comprises a reception circuit in the system for receiving the contents of the identification register, a storage circuit for storing the contents of the identification register, a determination circuit in the system for determining the contents of the storage circuit, such as a logic unit, and a clock halt circuit for stopping the clock. In this manner, various characteristics of the processor may be determined allowing the system to be reconfigured and power conserved appropriately.

摘要翻译： 计算机系统中的节能装置。 该装置包括处理器中的识别寄存器，其包括用于识别处理器的特性的多个标志的内容。 这些特征之一可以是处理器是否包括静态逻辑器件。 在这样的系统中，连接到处理器的时钟可以停止，而不会在处理器中损坏数据。 其他特征可以包括处理器是以与系统相同的速率计时，还是处理器是否可以在较低电压电源上操作。 该装置还包括传输电路，用于在接收到第一代码时将识别寄存器的内容从处理器传送到耦合到处理器的系统。 该装置还包括用于接收识别寄存器的内容的系统中的接收电路，用于存储识别寄存器的内容的存储电路，用于确定存储电路的内容的系统中的确定电路，例如逻辑 单元和用于停止时钟的时钟停止电路。 以这种方式，可以确定处理器的各种特性，允许系统被适当地重新配置和功率保存。

公开(公告)号：US07079420B2

公开(公告)日：2006-07-18

申请号：US10747217

申请日：2003-12-30

申请人： Assaf Shappir ,  Dror Avni ,  Boaz Eitan

发明人： Assaf Shappir ,  Dror Avni ,  Boaz Eitan

IPC分类号： G11C16/04

CPC分类号： G11C29/50 ,  G11C16/04 ,  G11C16/3436 ,  G11C16/3445 ,  G11C16/3459 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C29/50004

摘要： A method and a system for operating bits of memory cells in a memory array, the method including applying a first operating pulse to a terminal of a first cell, the first operating pulse is intended to place the first cell into a predefined state; and applying a second operating pulse to a terminal of a second cell in the set, the second operating pulse is intended to place the second cell to the predefined state, and the pulse characteristics of the second operating pulse are a function of the response of the first cell to the first operating pulse.

摘要翻译： 一种用于操作存储器阵列中的存储器单元的位的方法和系统，所述方法包括将第一操作脉冲施加到第一单元的端子，所述第一操作脉冲旨在将所述第一单元放置在预定状态; 以及将第二操作脉冲施加到所述组中的第二小区的终端，所述第二操作脉冲旨在将所述第二小区置于所述预定状态，并且所述第二操作脉冲的脉冲特性是所述第二操作脉冲的响应的函数 第一个电池到第一个工作脉冲。

公开(公告)号：US06928001B2

公开(公告)日：2005-08-09

申请号：US09730586

申请日：2000-12-07

申请人： Dror Avni ,  Boaz Eitan

发明人： Dror Avni ,  Boaz Eitan

IPC分类号： G11C16/02 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  G11C16/28 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C16/06

CPC分类号： G11C11/5671 ,  G11C16/0475 ,  G11C16/10 ,  G11C16/14 ,  G11C16/28 ,  G11C16/3468 ,  G11C16/3481

摘要： A method for programming and erasing a memory array includes the step of adapting programming or erase pulses to the current state of the memory array. In one embodiment, the step of adapting includes the steps of determining the voltage level of the programming pulse used to program a fast bit of the memory array and setting an initial programming level of the memory array to a level in the general vicinity of the programming level of the fast bit. For erasure, the method includes the steps of determining erase conditions of the erase pulse used to erase a slowly erasing bit of said memory array and setting initial erase conditions of said memory array to the general vicinity of said erase conditions of said slowly erasing bit. In another embodiment of the array, the step of adapting includes the steps of measuring the current threshold level of a bit to within a given range and selecting an incremental voltage level of a next programming or erase pulse for the bit in accordance with the measured current threshold level.

公开(公告)号：US5488639A

公开(公告)日：1996-01-30

申请号：US171554

申请日：1993-12-21

申请人： Peter D. MacWilliams ,  Dror Avni ,  Avi Liebermensch ,  Anan Baransy ,  Robert L. Farrell

发明人： Peter D. MacWilliams ,  Dror Avni ,  Avi Liebermensch ,  Anan Baransy ,  Robert L. Farrell

IPC分类号： H04L7/02 ,  H04L7/033 ,  H04L7/00

CPC分类号： H04L7/02 ,  H04L7/0338 ,  H04L7/0337

摘要： A method and apparatus for synchronizing an asynchronous signal to a clock signal. The apparatus includes an enable generator, first, second and third sampling circuits, a selecting circuit, and can include a latching circuit. The enable generator is coupled to the first sampling circuit by a first enable line, to the second sampling circuit by a second enable line, and to the third sampling circuit by a third enable line. The first, second, and third sampling circuits are coupled to receive the asynchronous signal. The selecting circuit is coupled to receive the output signals of the first, second and third sampling circuits. For the first sampling circuit, the following steps are performed: sampling the asynchronous signal, generating an output signal for the sampling circuit, waiting a period of time, and selecting the sampling circuit's output signal. These steps are also performed for the second sampling circuit and the third sampling circuit.

摘要翻译： 一种用于将异步信号同步到时钟信号的方法和装置。 该装置包括使能发生器，第一，第二和第三采样电路，选择电路，并且可以包括锁存电路。 使能发生器通过第一使能线耦合到第一采样电路，通过第二使能线耦合到第二采样电路，并通过第三使能线耦合到第三采样电路。 第一，第二和第三采样电路被耦合以接收异步信号。 选择电路被耦合以接收第一，第二和第三采样电路的输出信号。 对于第一采样电路，执行以下步骤：对异步信号进行采样，产生采样电路的输出信号，等待一段时间，并选择采样电路的输出信号。 对于第二采样电路和第三采样电路也执行这些步骤。

公开(公告)号：US20100146239A1

公开(公告)日：2010-06-10

申请号：US12330116

申请日：2008-12-08

申请人： Amir GABAI ,  Yoav Yogev ,  Dror Avni ,  Eli Lusky

发明人： Amir GABAI ,  Yoav Yogev ,  Dror Avni ,  Eli Lusky

IPC分类号： G06F12/10 ,  G06F11/20

CPC分类号： G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7202 ,  G11C29/76

摘要： The invention provides a method of managing bad block in a data storage device having an OTP memory die in order to present a continues address space toward the user, by using some of the OTP memory space for the management and maintaining address replacement table. Fast and efficient programming and writing algorithms are presented.

摘要翻译： 本发明提供了一种管理具有OTP存储器管芯的数据存储设备中的坏块的方法，以便通过使用一些OTP存储器空间来管理和维护地址替换表来向用户呈现持续的地址空间。 介绍了快速高效的编程和编写算法。

公开(公告)号：US07420848B2

公开(公告)日：2008-09-02

申请号：US11328015

申请日：2006-01-09

申请人： Assaf Shappir ,  Dror Avni ,  Boaz Eitan

发明人： Assaf Shappir ,  Dror Avni ,  Boaz Eitan

IPC分类号： G11C16/06 ,  G11C16/04

CPC分类号： G11C29/50 ,  G11C16/04 ,  G11C16/3436 ,  G11C16/3445 ,  G11C16/3459 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C29/50004

摘要： A method and a system for operating bits of memory cells in a memory array, the method including applying a first operating pulse to a terminal of a first cell, the first operating pulse is intended to place the first cell into a predefined state; and applying a second operating pulse to a terminal of a second cell in the set, the second operating pulse is intended to place the second cell to the predefined state, and the pulse characteristics of the second operating pulse are a function of the response of the first cell to the first operating pulse.

摘要翻译： 一种用于操作存储器阵列中的存储器单元的位的方法和系统，所述方法包括将第一操作脉冲施加到第一单元的端子，所述第一操作脉冲旨在将所述第一单元放置在预定状态; 以及将第二操作脉冲施加到所述组中的第二小区的终端，所述第二操作脉冲旨在将所述第二小区置于所述预定状态，并且所述第二操作脉冲的脉冲特性是所述第二操作脉冲的响应的函数 第一个电池到第一个工作脉冲。

公开(公告)号：US20060126396A1

公开(公告)日：2006-06-15

申请号：US11328015

申请日：2006-01-09

申请人： Assaf Shappir ,  Dror Avni ,  Boaz Eitan

发明人： Assaf Shappir ,  Dror Avni ,  Boaz Eitan

IPC分类号： G11C16/04

CPC分类号： G11C29/50 ,  G11C16/04 ,  G11C16/3436 ,  G11C16/3445 ,  G11C16/3459 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C29/50004

摘要： A method and a system for operating bits of memory cells in a memory array, the method including applying a first operating pulse to a terminal of a first cell, the first operating pulse is intended to place the first cell into a predefined state; and applying a second operating pulse to a terminal of a second cell in the set, the second operating pulse is intended to place the second cell to the predefined state, and the pulse characteristics of the second operating pulse are a function of the response of the first cell to the first operating pulse.

摘要翻译： 一种用于操作存储器阵列中的存储器单元的位的方法和系统，所述方法包括将第一操作脉冲施加到第一单元的端子，所述第一操作脉冲旨在将所述第一单元放置在预定状态; 以及将第二操作脉冲施加到所述组中的第二小区的终端，所述第二操作脉冲旨在将所述第二小区置于所述预定状态，并且所述第二操作脉冲的脉冲特性是所述第二操作脉冲的响应的函数 第一个电池到第一个工作脉冲。