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公开(公告)号：US5488639A
公开(公告)日：1996-01-30
申请号：US171554
申请日：1993-12-21
CPC分类号： H04L7/02 , H04L7/0338 , H04L7/0337
摘要： A method and apparatus for synchronizing an asynchronous signal to a clock signal. The apparatus includes an enable generator, first, second and third sampling circuits, a selecting circuit, and can include a latching circuit. The enable generator is coupled to the first sampling circuit by a first enable line, to the second sampling circuit by a second enable line, and to the third sampling circuit by a third enable line. The first, second, and third sampling circuits are coupled to receive the asynchronous signal. The selecting circuit is coupled to receive the output signals of the first, second and third sampling circuits. For the first sampling circuit, the following steps are performed: sampling the asynchronous signal, generating an output signal for the sampling circuit, waiting a period of time, and selecting the sampling circuit's output signal. These steps are also performed for the second sampling circuit and the third sampling circuit.
摘要翻译： 一种用于将异步信号同步到时钟信号的方法和装置。 该装置包括使能发生器，第一，第二和第三采样电路，选择电路，并且可以包括锁存电路。 使能发生器通过第一使能线耦合到第一采样电路，通过第二使能线耦合到第二采样电路，并通过第三使能线耦合到第三采样电路。 第一，第二和第三采样电路被耦合以接收异步信号。 选择电路被耦合以接收第一，第二和第三采样电路的输出信号。 对于第一采样电路，执行以下步骤：对异步信号进行采样，产生采样电路的输出信号，等待一段时间，并选择采样电路的输出信号。 对于第二采样电路和第三采样电路也执行这些步骤。
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2.发明授权Cache subsystem for microprocessor based computer system with synchronous and asynchronous data path 失效用于基于微处理器的计算机系统的缓存子系统，具有同步和异步数据路径
公开(公告)号：US5293603A
公开(公告)日：1994-03-08
申请号：US710079
申请日：1991-06-04
CPC分类号： G06F12/0864 , G06F12/0804 , G06F12/0835 , G06F12/0862 , G06F12/0897 , G06F2212/6082
摘要： An integrated circuit, for use as a cache subsystem, implements a cache static random access memory (SRAM) storage array, a central processor unit (CPU) bus interface and a main memory bus interface. The CPU bus and main memory bus interfaces include multiplexers, buffers, and local control for optimizing burst read and write operations to and from the CPU bus. These circuits allow a full cache line to be read or written in a single access of the SRAM array. Control logic is utilized within the CPU bus interface for controlling CPU bursts in the order defined by the CPU. The memory bus interface includes internal buffers used in performing memory bus reads, write-throughs, write-backs and snoops. Tracking logic is employed for determining the appropriate internal buffer to be utilized for a particular memory bus cycle. Additionally, a data path is included for transparently passing data between the CPU and memory bus interfaces without disturbance of the SRAM array.
摘要翻译： 用作缓存子系统的集成电路实现了高速缓存静态随机存取存储器（SRAM）存储阵列，中央处理器单元（CPU）总线接口和主存储器总线接口。 CPU总线和主存储器总线接口包括多路复用器，缓冲器和本地控制，用于优化对CPU总线的突发读和写操作。 这些电路允许在SRAM阵列的单个访问中读取或写入完整的高速缓存行。 控制逻辑用于CPU总线接口，用于按照CPU定义的顺序控制CPU脉冲串。 存储器总线接口包括用于执行存储器总线读取，写入，回写和监听的内部缓冲器。 跟踪逻辑用于确定要用于特定存储器总线周期的适当的内部缓冲器。 另外，包括数据路径，用于在CPU和存储器总线接口之间透明地传递数据，而不会对SRAM阵列造成干扰。
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3.发明授权Cache memory integrated circuit for use with a synchronous central processor bus and an asynchronous memory bus 失效与同步中央处理器总线和异步存储器总线一起使用的高速缓存存储器集成电路
公开(公告)号：US5228134A
公开(公告)日：1993-07-13
申请号：US710075
申请日：1991-06-04
IPC分类号： G06F12/08 , G11C11/401
CPC分类号： G06F12/0879
摘要： An integrated circuit implements a cache static random access memory (SRAM) storage element which includes a central processor unit (CPU) bus interface incorporating multiplexers and buffers circuits for optimizing burst read and write operations across the CPU bus. Theses circuits allow a full cache line to be read/written in a single access of the SRAM array. Control logic is utilized within the CPU bus interface for controlling CPU bursts in the order defined by the CPU. The memory bus interface includes internal buffers used in performing memory bus reads, write-throughs, write-backs and snoops. Tracking logic is employed for determining the appropriate internal buffer to be utilized for a particular memory bus cycle. Additionally, a data path is included for transparently passing data between the CPU and memory bus interfaces without disturbance of the SRAM array.
摘要翻译： 集成电路实现了高速缓存静态随机存取存储器（SRAM）存储元件，其包括集成有多路复用器和缓冲器电路的中央处理器单元（CPU）总线接口，用于优化跨CPU总线的突发读和写操作。 这些电路允许在SRAM阵列的单个访问中读取/写入完整的高速缓存行。 控制逻辑用于CPU总线接口，用于按照CPU定义的顺序控制CPU脉冲串。 存储器总线接口包括用于执行存储器总线读取，写入，回写和监听的内部缓冲器。 跟踪逻辑用于确定要用于特定存储器总线周期的适当的内部缓冲器。 另外，包括数据路径，用于在CPU和存储器总线接口之间透明地传递数据，而不会对SRAM阵列造成干扰。
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公开(公告)号：US5355467A
公开(公告)日：1994-10-11
申请号：US208090
申请日：1994-03-08
CPC分类号： G06F12/0811 , G06F12/0831 , G06F2212/6082
摘要： A second level cache memory controller, implemented as an integrated circuit unit, operates in conjunction with a secondary random access cache memory and a main memory (system) bus controller to form a second level cache memory subsystem. The subsystem is interfaced to the local processor (CPU) bus and to the main memory bus providing independent access by both buses, thereby reducing traffic of the main memory bus when the data required by the CPU is located in secondary cache. Similarly, CPU bus traffic is minimized when secondary cache access by the main memory bus for snoops and write-backs to main memory. Snoop latches interfaced with the main memory bus provide snoop access to the cache memory via the cache directory in the secondary cache controller unit. The controller also supports parallel look-up in the controller tag array and the secondary cache using most-recently-used (MRU) main memory write-through and pipelining of memory bus cycle requests.
摘要翻译： 实现为集成电路单元的第二级高速缓冲存储器控制器与辅助随机存取高速缓冲存储器和主存储器（系统）总线控制器一起操作以形成第二级高速缓存存储器子系统。 该子系统与本地处理器（CPU）总线和主存储器总线接口，由总线提供独立的访问，从而当CPU所需的数据位于二级缓存中时，减少主存储器总线的流量。 类似地，当主存储器总线的二级缓存访问被窃听并回写到主存储器时，CPU总线流量被最小化。 与主存储器总线连接的监听锁存器通过次级高速缓存控制器单元中的高速缓存目录提供对高速缓冲存储器的窥探访问。 控制器还支持使用最近使用（MRU）主存储器直写和流水线存储器总线周期请求的控制器标签阵列和二级缓存中的并行查找。
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公开(公告)号：US08205032B2
公开(公告)日：2012-06-19
申请号：US13069690
申请日：2011-03-23
CPC分类号： G06F9/30043 , G06F9/3017 , G06F9/3851
摘要： Embodiments of apparatuses, methods, and systems for decoding a virtual machine control structure identification are disclosed. In one embodiment, an apparatus includes a virtual machine control structure to decode a virtual machine control structure identification data. The virtual machine control structure identification data is decoded into an address of a virtual machine control structure field and an offset. The offset is to help identify a micro-operation associated with a virtual machine architecture instruction to be executed.
摘要翻译： 公开了用于解码虚拟机控制结构标识的装置，方法和系统的实施例。 在一个实施例中，一种装置包括用于解码虚拟机控制结构标识数据的虚拟机控制结构。 虚拟机控制结构识别数据被解码成虚拟机控制结构字段的地址和偏移量。 补偿是帮助识别与要执行的虚拟机架构指令相关的微操作。
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公开(公告)号：US20110173613A1
公开(公告)日：2011-07-14
申请号：US13069690
申请日：2011-03-23
IPC分类号： G06F9/455
CPC分类号： G06F9/30043 , G06F9/3017 , G06F9/3851
摘要： Embodiments of apparatuses, methods, and systems for decoding a virtual machine control structure identification are disclosed. In one embodiment, an apparatus includes a virtual machine control structure to decode a virtual machine control structure identification data. The virtual machine control structure identification data is decoded into an address of a virtual machine control structure field and an offset. The offset is to help identify a micro-operation associated with a virtual machine architecture instruction to be executed.
摘要翻译： 公开了用于解码虚拟机控制结构标识的装置，方法和系统的实施例。 在一个实施例中，一种装置包括用于解码虚拟机控制结构标识数据的虚拟机控制结构。 虚拟机控制结构识别数据被解码成虚拟机控制结构字段的地址和偏移量。 补偿是帮助识别与要执行的虚拟机架构指令相关的微操作。
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公开(公告)号：US20100031268A1
公开(公告)日：2010-02-04
申请号：US12221083
申请日：2008-07-31
IPC分类号： G06F9/46
CPC分类号： G06F9/3851 , G06F9/30087 , G06F9/3836 , G06F9/3838 , G06F9/3857
摘要： Techniques are described that can be used to ensure ordered computation and/or retirement of threads in a multithreaded environment. Threads may contain bundled instances of work, each with unique ordering restrictions relative to other instances of work packaged in other threads in the system. When applied to 3D graphics, video and image processing domains allow unrestricted processing of threads until reaching their critical sections. Ordering may be required prior to executing critical sections and beyond.
摘要翻译： 描述了可用于确保多线程环境中线程的有序计算和/或退出的技术。 线程可能包含捆绑的工作实例，每个实例具有相对于系统中其他线程打包的其他工作实例的独特排序限制。 当应用于3D图形时，视频和图像处理域允许不受限制地处理线程直到到达其关键部分。 执行关键部分之前可能需要订购。
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8.发明授权公开(公告)号：US09035959B2
公开(公告)日：2015-05-19
申请号：US12057601
申请日：2008-03-28
申请人： Zeev Offen , Ariel Berkovits , Thomas A. Piazza , Robert L. Farrell , Altug Koker , Opher Kahn
发明人： Zeev Offen , Ariel Berkovits , Thomas A. Piazza , Robert L. Farrell , Altug Koker , Opher Kahn
CPC分类号： G06F12/0831 , G06F12/0811 , G06F12/0822 , G06F12/0828 , G06F12/0835 , G06F13/1668 , G06F13/28 , G06F13/4282 , G06F2212/283 , G06F2212/60 , G06F2212/621 , G06F2213/0026 , G06T1/60 , G11C7/1072
摘要： A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.
摘要翻译： 一种能够在不同高速缓存一致性域内的代理之间进行信息共享的技术。 在一个实施例中，图形设备可以使用由一个或多个处理核心使用的一个或多个高速缓存来存储或读取信息，这些信息可以由一个或多个处理核心以不影响与编程相关的编程和一致性规则的方式来访问 图形设备。
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公开(公告)号：US06785829B1
公开(公告)日：2004-08-31
申请号：US09608160
申请日：2000-06-30
申请人： Varghese George , Robert L. Farrell
发明人： Varghese George , Robert L. Farrell
IPC分类号： G06F132
CPC分类号： G06F1/3296 , G06F1/08 , G06F1/26 , G06F1/3203 , G06F1/324 , Y02D10/126 , Y02D10/172 , Y02D50/20
摘要： A power control circuit an corresponding technique for adjusting operating frequency and/or supply voltage in sections of a single electronic device while maintaining substantially constant operating frequency and/or supply voltage in the other sections in the electronic device. Such control is based on the operating environment of the hardware product employing the electronic device by determining whether the hardware product is connected to an external power source. As a result, the electronic device in the hardware product is able to operate at full frequency and voltage during certain situations and to operate at a reduced frequency and/or voltage in some sections of the processor and not in the other sections during other situations.
摘要翻译： 一种功率控制电路，用于在单个电子设备的部分中调节工作频率和/或电源电压，同时在电子设备中的其它部分保持基本恒定的工作频率和/或电源电压的相应技术。 这种控制是基于通过确定硬件产品是否连接到外部电源的采用电子设备的硬件产品的操作环境。 结果，硬件产品中的电子设备能够在某些情况下以全频率和电压工作，并且在处理器的某些部分中以不降低的频率和/或电压工作，而在其他情况下不在其他部分。
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10.发明授权Integrating data scaling and buffering functions to minimize memory requirement 失效集成数据缩放和缓冲功能以最大限度地减少内存需求
公开(公告)号：US6091426A
公开(公告)日：2000-07-18
申请号：US887415
申请日：1997-07-03
IPC分类号： G09G5/00
CPC分类号： G06T3/4023
摘要： A scaling circuit residing on a single silicon substrate includes a buffer for storing a plurality of partially scaled data. A multiplier is provided for multiplying a weight signal with each of a plurality of input data to produce a plurality of weighted data. An adder is coupled to (1) the multiplier and (2) the buffer for adding each of the weighted data to one of the partially scaled data to produce a plurality of scaled data. When a first one of the scaled data is produced by the adder, the first one of the scaled data can remain in the buffer until displaced by a new data to be scaled such that the scaling circuit is directly coupled to an external bus without requiring any external buffering memory coupled in between. A method for scaling a block of data and transferring the scaled data to the bus is also described.
摘要翻译： 驻留在单个硅衬底上的缩放电路包括用于存储多个部分缩放的数据的缓冲器。 提供了一个乘法器，用于将加权信号与多个输入数据中的每一个相乘以产生多个加权数据。 加法器耦合到（1）乘法器和（2）用于将每个加权数据加到部分缩放数据之一中以产生多个缩放数据的缓冲器。 当加法器产生缩放数据中的第一个时，缩放数据中的第一个可以保留在缓冲器中，直到被要缩放的新数据移位，使得缩放电路直接耦合到外部总线，而不需要任何 耦合在其间的外部缓冲存储器。 还描述了用于缩放数据块并将缩放的数据传送到总线的方法。
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