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    Interference matrix construction
    5.
    发明授权
    Interference matrix construction 有权
    干扰矩阵构造

    公开(公告)号：US07577186B2

    公开(公告)日：2009-08-18

    申请号：US10935015

    申请日：2004-09-07

    申请人： John K. Thomas ,  Anand P. Narayan ,  Eric S. Olson

    发明人： John K. Thomas ,  Anand P. Narayan ,  Eric S. Olson

    IPC分类号： H04B1/00

    CPC分类号： H04B1/7105 ,  H04B1/7107 ,  H04B1/7117

    摘要： The present invention provides systems and methods for interference matrix construction. Such an interference matrix may be used to generate a cancellation operator that when applied to a signal may substantially remove selected interfering signals. In one embodiment of the invention, a system comprises an interference selector configured for selecting one or more interferers for interference cancellation. The system also comprises a matrix generator communicatively coupled to the interference selector and configured for receiving selected interferers from the interference selector. The matrix generator is also configured for generating a matrix having one or more vectors, wherein each vector comprises elements of at least one of the selected interferers. Such an interference matrix and the subsequent generation of the cancellation operator may advantageously provide interference cancellation to systems employing CDMA (e.g., such as cdmaOne and cdma2000), WCDMA, Broadband CDMA, UMTS and GPS signals.

    摘要翻译： 本发明提供了干涉矩阵构造的系统和方法。 这样的干涉矩阵可以用于产生消除操作者，当应用于信号时，可以基本上去除所选择的干扰信号。 在本发明的一个实施例中，系统包括被配置用于选择一个或多个干扰源用于干扰消除的干扰选择器。 该系统还包括通信地耦合到干扰选择器并被配置为从干扰选择器接收所选择的干扰源的矩阵发生器。 矩阵生成器还被配置用于生成具有一个或多个向量的矩阵，其中每个向量包括所选择的干扰源中的至少一个的元素。 这样的干扰矩阵和随后的取消算子的产生可以有利地对采用CDMA（例如cdmaOne和cdma2000），WCDMA，宽带CDMA，UMTS和GPS信号的系统提供干扰消除。

    Serial cancellation receiver design for a coded signal processing engine
    6.
    发明授权
    Serial cancellation receiver design for a coded signal processing engine 有权
    编码信号处理引擎的串行消除接收机设计

    公开(公告)号：US07359465B2

    公开(公告)日：2008-04-15

    申请号：US11103138

    申请日：2005-04-11

    申请人： Eric S. Olson ,  Anand P. Narayan ,  John K. Thomas

    发明人： Eric S. Olson ,  Anand P. Narayan ,  John K. Thomas

    IPC分类号： H03D1/04

    CPC分类号： H04B1/7105 ,  H04B1/7075 ,  H04B1/709 ,  H04B1/7103 ,  H04B1/7117 ,  H04B2001/70706 ,  H04B2201/70701 ,  H04B2201/70715

    摘要： A novel serial receiver for a wireless communication system is provided. The communication system comprises: a receiver for receiving a signal y having data parameters; a control processor; the control processor for receiving the signal y and the data parameters; at least two fingers, the control processor for determining which of the data parameters are sent to respective fingers, wherein the at least two fingers have at least a search finger and a tracking finger; and wherein the tracking finger comprises a correlator and a Coded Signal Processing Engine (CSPE), the CSPE for interference cancellation in the reception of the signal y. In addition, numerous other embodiments of the serial receiver are provided along with methods for using the serial receiver.

    摘要翻译： 提供了一种用于无线通信系统的新型串行接收机。 通信系统包括：接收器，用于接收具有数据参数的信号y; 一个控制处理器; 用于接收信号y和数据参数的控制处理器; 至少两个手指，所述控制处理器用于确定哪个数据参数被发送到各个手指，其中所述至少两个手指至少具有搜索指和跟踪指; 并且其中所述跟踪指包括相关器和编码信号处理引擎（CSPE），所述CSPE用于在接收信号y时进行干扰消除。 此外，提供串行接收机的许多其它实施例以及使用串行接收机的方法。

    Serial cancellation receiver design for a coded signal processing engine
    7.
    发明授权
    Serial cancellation receiver design for a coded signal processing engine 有权
    编码信号处理引擎的串行消除接收机设计

    公开(公告)号：US08374299B2

    公开(公告)日：2013-02-12

    申请号：US13076332

    申请日：2011-03-30

    申请人： Eric S. Olson ,  Anand P. Narayan ,  John K. Thomas

    发明人： Eric S. Olson ,  Anand P. Narayan ,  John K. Thomas

    IPC分类号： H03D1/04

    CPC分类号： H04B1/7105 ,  H04B1/7075 ,  H04B1/709 ,  H04B1/7103 ,  H04B1/7117 ,  H04B2001/70706 ,  H04B2201/70701 ,  H04B2201/70715

    摘要： An interference cancelling receiver combines data from multiple paths after aligning to transmitter timing, and uses either an equalizer or a Rake receiver to compute symbol estimates. Interference estimates are generated from the symbol estimates, and multiple interference estimates are combined after re-aligning the interference estimates to receiver timing. At least two segments of symbol estimates are computed for each segment of interference cancelled data.Various techniques may be employed for controlling the latency and sequencing of these operations, and the subsystems within the canceller may use different processing clock speeds.

    摘要翻译： 干扰消除接收机在对准发射机定时之后组合来自多个路径的数据，并且使用均衡器或Rake接收机来计算符号估计。 从符号估计产生干扰估计，并且在将干扰估计重新对准接收机定时之后组合多个干扰估计。 对干扰消除数据的每个段计算符号估计的至少两个段。 可以采用各种技术来控制这些操作的等待时间和顺序，并且消除器内的子系统可以使用不同的处理时钟速度。

    Systems and methods for control of advanced receivers
    8.
    发明授权
    Systems and methods for control of advanced receivers 有权
    高级接收机控制系统和方法

    公开(公告)号：US08179946B2

    公开(公告)日：2012-05-15

    申请号：US12274551

    申请日：2008-11-20

    申请人： Brian Lee Roberts ,  Kenneth C Grobaski ,  Anand P Narayan

    发明人： Brian Lee Roberts ,  Kenneth C Grobaski ,  Anand P Narayan

    IPC分类号： H04B1/00

    CPC分类号： H04B1/7117

    摘要： A controller for advanced receivers configures a plurality of advanced receiver modules based on figures of merit computed on the input signal. The controller also selects the appropriate output signal based on figures of merit of either the input or the output signals. The controller decisions can also be made in a bursty manner, where only a subset of the decisions to be made are made at a given time, thereby limiting the processing load of the control processor.

    摘要翻译： 用于高级接收器的控制器基于在输入信号上计算的品质因数配置多个高级接收器模块。 控制器还根据输入或输出信号的品质因数选择合适的输出信号。 控制器决定还可以以突发方式进行，其中仅在给定时间做出要作出的决定的子集，从而限制控制处理器的处理负担。

    Serial cancellation receiver design for a coded signal processing engine
    10.
    发明申请
    Serial cancellation receiver design for a coded signal processing engine 有权
    编码信号处理引擎的串行消除接收机设计

    公开(公告)号：US20110182330A1

    公开(公告)日：2011-07-28

    申请号：US13076332

    申请日：2011-03-30

    申请人： Eric S. Olson ,  Anand P. Narayan ,  John K. Thomas

    发明人： Eric S. Olson ,  Anand P. Narayan ,  John K. Thomas

    IPC分类号： H04B1/10

    CPC分类号： H04B1/7105 ,  H04B1/7075 ,  H04B1/709 ,  H04B1/7103 ,  H04B1/7117 ,  H04B2001/70706 ,  H04B2201/70701 ,  H04B2201/70715

    摘要： An interference cancelling receiver combines data from multiple paths after aligning to transmitter timing, and uses either an equalizer or a Rake receiver to compute symbol estimates. Interference estimates are generated from the symbol estimates, and multiple interference estimates are combined after re-aligning the interference estimates to receiver timing. At least two segments of symbol estimates are computed for each segment of interference cancelled data.Various techniques may be employed for controlling the latency and sequencing of these operations, and the subsystems within the canceller may use different processing clock speeds.

    摘要翻译： 干扰消除接收机在对准发射机定时之后组合来自多个路径的数据，并且使用均衡器或Rake接收机来计算符号估计。 从符号估计产生干扰估计，并且在将干扰估计重新对准接收机定时之后组合多个干扰估计。 对干扰消除数据的每个段计算符号估计的至少两个段。 可以采用各种技术来控制这些操作的等待时间和顺序，并且消除器内的子系统可以使用不同的处理时钟速度。